CMOS Readout Research Articles

A 0.23- $\mu \text{g}$ Bias Instability and 1- $\mu \text{g}/\surd $ Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout circuit architecture. A phase lock loop (PLL) with a hybrid and antinoise folding PFD is employed to sustain the oscillation of the MEMS oscillator, and the oscillation amplitude is set by an external reference. In addition, a sigma-delta frequency-to-digital converter is combined with the PLL to digitize the accelerometer’s frequency output for low power consumption. The MEMS transducer and the readout circuit are fabricated in an 80- $\mu \text{m}$ SOI and standard 0.35- $\mu \text{m}$ CMOS process, respectively. The SOA achieves 0.23- $\mu \text{g}$ bias instability and 1- $\mu \text{g}$ /Hz $^{1/2}$ acceleration noise density with a ±30 g full-scale, which are equivalent to 4-ppb relative instability and 17-ppb/Hz $^{1/2}$ relative acceleration noise density. It only consumes 2.7 mW under a 1.5 V supply.

Performance of Hg1−xCdxTe infrared focal plane array at elevated temperature

The simulated optical and electrical performance of the infrared HgCdTe focal plane array (FPA) for elevated operation temperature is reported. The depleted absorber layer is explored for equilibrium mode of operation up to 160 K. A resonant cavity is created to improve photon-matter interaction and hence, reduces the required absorption volume. The volume of the active region of HgCdTe detector is reduced by 70% in this manner. Dark current density is decreased without compromising the quantum efficiency. The effect of the reduced band filling effect leading to higher absorption coefficient and more efficient utilization of incident flux is employed. High quantum efficiency is achieved in a thin compositionally graded n+/ν/π/p HgCdTe photo-diode. This architecture helps to minimize the requirement of charge handling capacity in the CMOS read-out integrated circuit (ROIC) as the operation temperature is increased. Quantum efficiency ∼30% or above is shown to be sufficient for Noise Equivalent Temperature Difference (NETD) less than 20 mK with the reported design.

A CMOS-based high resolution fluoroscope (HRF) detector prototype with 49.5 μm pixels for use in endovascular image guided interventions (EIGI).

X-ray detectors to meet the high-resolution requirements for endovascular image-guided interventions (EIGIs) are being developed and evaluated. A new 49.5-micron pixel prototype detector is being investigated and compared to the current suite of high-resolution fluoroscopic (HRF) detectors. This detector featuring a 300-micron thick CsI(Tl) scintillator, and low electronic noise CMOS readout is designated the HRF-CMOS50. To compare the abilities of this detector with other existing high resolution detectors, a standard performance metric analysis was applied, including the determination of the modulation transfer function (MTF), noise power spectra (NPS), noise equivalent quanta (NEQ), and detective quantum efficiency (DQE) for a range of energies and exposure levels. The advantage of the smaller pixel size and reduced blurring due to the thin phosphor was exemplified when the MTF of the HRF-CMOS50 was compared to the other high resolution detectors, which utilize larger pixels, other optical designs or thicker scintillators. However, the thinner scintillator has the disadvantage of a lower quantum detective efficiency (QDE) for higher diagnostic x-ray energies. The performance of the detector as part of an imaging chain was examined by employing the generalized metrics GMTF, GNEQ, and GDQE, taking standard focal spot size and clinical imaging parameters into consideration. As expected, the disparaging effects of focal spot unsharpness, exacerbated by increasing magnification, degraded the higher-frequency performance of the HRF-CMOS50, while increasing scatter fraction diminished low-frequency performance. Nevertheless, the HRF-CMOS50 brings improved resolution capabilities for EIGIs, but would require increased sensitivity and dynamic range for future clinical application.

Ge0.975Sn0.025 320 × 256 imager chip for 1.6-1.9 μm infrared vision.

We report the experimental fabrication and testing of a GeSn-based 320×256 image sensor focal plane array operating at -15°C in the 1.6-1.9μm spectral range. For image readout, the 2D pixel array of Ge/GeSn/Ge p-i-n heterophotodiodes was flip-chip bonded to a customized silicon CMOS readout integrated circuit. The resulting camera chip was operated using back-side illumination. Successful imaging of a tungsten-filament light bulb was attained with observation of gray-scale "hot spot" infrared features not seen using a visible-light camera. The Ge wafer used in the present imaging array will be replaced in future tests by a germanium-on-silicon wafer offering thin-film Ge upon Si or on SiO2/Si. This is expected to increase the infrared responsivity obtained in back-side illumination, and it will allow an imager in a Si-based foundry to be manufactured. Our experiments are a significant step toward the realization of group IV near-mid-infrared imaging systems, such as those for night vision.

Compact heterodyne NEMS oscillator for sensing applications

We present a novel topology of heterodyne nanoelectromechanical self-oscillator, aimed at the dense integration of resonator arrays for sensing applications. This oscillator is based on an original measurement method, suitable for both open loop and closed loop operations, which simplifies current down-mixing set-ups. When implemented on-chip, it will allow the reduction of the size and power consumption of readout CMOS circuitry. This is today the limiting factor for the integration density of NEMS oscillators for real-life applications. Here we characterize this method in both open-loop and closed-loop, and evaluate its frequency stability.

A 2D imager for X-ray FELs with a 65 nm CMOS readout based on per-pixel signal compression and 10 bit A/D conversion

A readout channel for applications to X-ray diffraction imaging at free electron lasers has been developed in a 65nm CMOS technology. The analog front-end circuit can achieve an input dynamic range of 100dB by leveraging a novel signal compression technique based on the non-linear features of MOS capacitors. Trapezoidal shaping is accomplished through a transconductor and a switched capacitor circuit, performing gated integration and correlated double sampling. A small area, low power 10bit successive approximation register (SAR) ADC, operated in a time-interleaved fashion, is used for numerical conversion of the amplitude measurement. Operation at 5MHz of the analog channel including the shaper was demonstrated. Also, the channel was found to be compliant with single 1keV photon resolution at 1.25MHz. The ADC provides a signal-to-noise ratio (SNR) of 56dB, corresponding to an equivalent number of bits (ENOB) of 9bits, and a differential non linearity DNL<1 LSB at a sampling rate slightly larger than 1.8MHz.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

Quantitative comparison using Generalized Relative Object Detectability (G-ROD) metrics of an amorphous selenium detector with high resolution Microangiographic Fluoroscopes (MAF) and standard flat panel detectors (FPD).

A novel amorphous selenium (a-Se) direct detector with CMOS readout has been designed, and relative detector performance investigated. The detector features include a 25μm pixel pitch, and 1000μm thick a-Se layer operating at 10V/μm bias field. A simulated detector DQE was determined, and used in comparative calculations of the Relative Object Detectability (ROD) family of prewhitening matched-filter (PWMF) observer and non-prewhitening matched filter (NPWMF) observer model metrics to gauge a-Se detector performance against existing high resolution micro-angiographic fluoroscopic (MAF) detectors and a standard flat panel detector (FPD). The PWMF-ROD or ROD metric compares two x-ray imaging detectors in their relative abilities in imaging a given object by taking the integral over spatial frequencies of the Fourier transform of the detector DQE weighted by an object function, divided by the comparable integral for a different detector. The generalized-ROD (G-ROD) metric incorporates clinically relevant parameters (focal-spot size, magnification, and scatter) to show the degradation in imaging performance for detectors that are part of an imaging chain. Preliminary ROD calculations using simulated spheres as the object predicted superior imaging performance by the a-Se detector as compared to existing detectors. New PWMF-G-ROD and NPWMF-G-ROD results still indicate better performance by the a-Se detector in an imaging chain over all sphere sizes for various focal spot sizes and magnifications, although a-Se performance advantages were degraded by focal spot blurring. Nevertheless, the a-Se technology has great potential to provide breakthrough abilities such as visualization of fine details including of neuro-vascular perforator vessels and of small vascular devices.

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below \(\sim \)4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to \(\sim \)200 \(\upmu \)m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Theoretical investigation on input properties of DI and CTIA readout integrated circuit

Advanced hybrid infrared focal plane arrays consist of a semiconductor photodetector chip bump-bonded to a silicon CMOS readout integrated circuit (ROIC). Among a number of readout structures of ROICs, the direct injection (DI) and the capacitor feedback transimpedance amplifier (CTIA) are widely used. In this paper the input properties, especially injection efficiency, of DI and CTIA are discussed respectively based on their structures. The injection efficiency of DI is relevant to injection current and is low at small background photocurrent; however, the DI enables an ultralow power consumption due to its simple structure. The injection efficiency of the CTIA is independent of injection current and is high even at low background photocurrent, but the power dissipation of the CTIA is comparatively higher than that of the DI due to its more complex structure.

Development for Germanium Blocked Impurity Band Far-Infrared Image Sensors with Fully-Depleted Silicon-On-Insulator CMOS Readout Integrated Circuit

We are developing far-infrared (FIR) imaging sensors for low-background and high-sensitivity applications such as infrared astronomy. Previous FIR monolithic imaging sensors, such as an extrinsic germanium photo-conductor (Ge PC) with a PMOS readout integrated circuit (ROIC) hybridized by indium pixel-to-pixel interconnection, had three difficulties: (1) short cut-off wavelength (120 \(\upmu \)m), (2) large power consumption (10 \(\upmu \)W/pixel), and (3) large mismatch in thermal expansion between the Ge PC and the Si ROIC. In order to overcome these difficulties, we developed (1) a blocked impurity band detector fabricated by a surface- activated bond technology, whose cut-off wavelength is longer than 160 \(\upmu \)m, (2) a fully-depleted silicon-on-insulator CMOS ROIC which works below 4 K with 1 \(\upmu \)W/pixel operating power, and (3) a new concept, Si-supported Ge detector, which shows tolerance to thermal cycling down to 3 K. With these new techniques, we are now developing a \(32 \times 32 \) FIR imaging sensor.

Development of a Standardised Readout System for Active Pixel Sensors in HV/HR-CMOS Technologies for ATLAS Inner Detector Upgrades

The LHC Phase-II Upgrade results in new challenges for tracking detectors for example in terms of cost effectiveness, resolution and radiation hardness. Active Pixel Sensors in HV/HR-CMOS technologies show promising results coping with these challenges. In order to demonstrate the feasibility of hybrid modules with active CMOS sensors and readout chips for the future ATLAS Inner Tracker, ATLAS R&D activities have started. After introducing the basic concepts and the demonstrator program, the development of an ATLAS compatible readout system will be presented as well as tuning procedures and measurements with demonstrator modules to test the readout system.

CMOS Pixel Spectroscopic Circuits for Cd(Zn)Te Gamma Ray Imagers

A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

X-ray characterization of a multichannel smart-pixel array detector.

The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 × 48 pixels, each 130 µm × 130 µm × 520 µm thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gating time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.

High-speed CMOS readout integrated circuit for small-pixel-size microbolometric focal plane array

Abstract A novel kind of high-speed CMOS readout integrated circuit for large-scale microbolometric focal plane array is proposed in this paper. The proposed readout integrated circuit can directly amplify the voltage signals of all microbolometric pixels in focal plane array response to infrared irradiation and then output the amplified voltage signals column by column and row by row. Because there is no need of photo-generated current integration capacitor for microbolometric voltage response, the readout integrated circuit can save a lot of readout circuit area for small-pixel-size. In addition, the proposed CMOS readout integrated circuit can produce an output of the sensing voltage signals of microbolometer array at very high speed for which there is no integration time consumption when the microbolometric focal plane array operates.

A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications

Mid-wavelength infrared (MWIR) thermography is an emerging technology with promising applications such as industrial monitoring, medicine and automotive, but its use in high-speed cameras is not yet widespread due to the lack of inexpensive sensor integration solutions and their common reliance on bulky cooling mechanisms. This work fills the gap by presenting a monolithic uncooled high-speed imager based on vapor-phase deposition lead selenide (VPD PbSe) photoconductors and a fully digital and configurable CMOS read-out integrated circuit (ROIC) to operate the MWIR imager. This ROIC features cancellation of PbSe dark current, compensation of its output capacitance and correction of the fixed pattern noise (FPN) caused by process non-uniformities in CMOS fabrication and detector deposition. The low-cost 80 × 80 imager has been integrated using 0.35 µm 2P4M standard CMOS technology and PbSe detector post-processing with 135 µm pixel pitch and 68% fill factor values. Experimental opto-electrical performance exhibits 10 bit real-time FPN compensation and DR calibration over the entire focal plane operating at 2 kfps, sub-0.5 LSB inter-pixel crosstalk, sub-µW pixel power consumption, and an overall figure of merit of 55 mK × ms.

A CMOS Readout With High-Precision and Low-Temperature-Coefficient Background Current Skimming for Infrared Focal Plane Array

A high-performance CMOS readout structure employing a new background current skimming technique for infrared focal plane array (IFPA) applications is proposed, analyzed, and verified. Both the background current skimming circuit and bias circuit have good immunity to threshold voltage variations. In addition, the background current skimming circuit is also independent of temperature variations. An experimental readout chip has been fabricated using SMIC 0.18- $\mu \text{m}$ 1P6M process technology with a unit-cell size of $30~\mu {\rm m} \times 27~\mu \text{m}$ and a power consumption less than 0.06 mW. With 4 V power supply, the readout integrated circuit provides a dynamic output range over 3 V and an output linearity of >99%. The background suppression current whose level is tunable between 470 nA and 5 $\mu \text{A}$ has a variation of 2.2%, corresponding to a temperature coefficient of 275 ppm/°C. The simulation and experimental results confirmed the good performance of the proposed background current skimming circuit for IFPA applications.

Analysis of electron multiplying charge coupled device and scientific CMOS readout noise models for Shack–Hartmann wavefront sensor accuracy

In recent years, detectors with subelectron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: electron multiplying charge coupled device (EMCCD) and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also find that the commonly used simple models for sCMOS readout noise are optimistic, and we recommend that a proper treatment of the sCMOS root mean square readout noise probability distribution should be considered during instrument performance modeling and development.

WE‐G‐204‐05: Relative Object Detectability Evaluation of a New High Resolution A‐Se Direct Detection System Compared to Indirect Micro‐Angiographic Fluoroscopic (MAF) Detectors

Purpose:To evaluate the task specific imaging performance of a new 25µm pixel pitch, 1000µm thick amorphous selenium direct detection system with CMOS readout for typical angiographic exposure parameters using the relative object detectability (ROD) metric.Methods:The ROD metric uses a simulated object function weighted at each spatial frequency by the detectors’ detective quantum efficiency (DQE), which is an intrinsic performance metric. For this study, the simulated objects were aluminum spheres of varying diameter (0.05–0.6mm). The weighted object function is then integrated over the full range of detectable frequencies inherent to each detector, and a ratio is taken of the resulting value for two detectors. The DQE for the 25µm detector was obtained from a simulation of a proposed a‐Se detector using an exposure of 200µR for a 50keV x‐ray beam. This a‐Se detector was compared to two microangiographic fluoroscope (MAF) detectors [the MAF‐CCD with pixel size of 35µm and Nyquist frequency of 14.2 cycles/mm and the MAF‐CMOS with pixel size of 75µm and Nyquist frequency of 6.6 cycles/mm] and a standard flat‐panel detector (FPD with pixel size of 194µm and Nyquist frequency of 2.5cycles/mm).Results:ROD calculations indicated vastly superior performance by the a‐Se detector in imaging small aluminum spheres. For the 50µm diameter sphere, the ROD values for the a‐Se detector compared to the MAF‐CCD, the MAF‐CMOS, and the FPD were 7.3, 9.3 and 58, respectively. Detector performance in the low frequency regime was dictated by each detector's DQE(0) value.Conclusion:The a‐Se with CMOS readout is unique and appears to have distinctive advantages of incomparable high resolution, low noise, no readout lag, and expandable design. The a‐Se direct detection system will be a powerful imaging tool in angiography, with potential break‐through applications in diagnosis and treatment of neuro‐vascular disease.Supported by NIH Grant: 2R01EB002873 and an equipment grant from Toshiba Medical Systems Corporation

Monolithic arrays of SDDs and low noise CMOS readout for X-ray spectroscopy measurements in nuclear physics experiments

This work deals with the development of Silicon Drift Detectors (SDDs) of different sizes and low noise CMOS read-out preamplifiers in view of their use in nuclear physics experiments, like the SIDDHARTA upgrade supported by Italian INFN. In this work we report about the recent SDDs and CMOS preamplifiers development, with particular emphasis on X-ray measurements at cryogenic temperatures. The SDDs presented are designed as single square shaped units of different areas 64 mm2 (8mm × 8mm) or 144 mm2 (12mm × 12mm) and also as monolithic arrays of 9 elements (8mm × 8mm each, total area 26mm × 26mm) in a3 × 3 format. The detectors have been designed and manufactured by the Fondazione Bruno Kessler (FBK). The read-out of the SDDs is based on the CMOS preamplifier (CUBE) for both the single unit and the 3 × 3 array. The CMOS technology is intrinsically more robust at lower temperatures with respect to the more conventional JFET transistor used in SDDs readout. A measured resolution of 123 eV on the Mn-Kα line with the optimum shaping time and a resolution of 126.4 eV with 250 ns shaping time have been obtained with round shaped 10 mm2 SDDs detectors. This last result leads to excellent spectroscopy performances even with very high input count rates making the SDD+CUBE combination very attractive also for synchrotron applications. The nine detectors array in addition to the preamplifiers the use of a multichannel ASIC for signal shaping and peak detection of all the units and of a custom Data Acquisition System. Also preliminary measurements of low energies lines are reported in order to prove the possibility of soft X-ray detection.