A 0.23- $\mu \text{g}$ Bias Instability and 1- $\mu \text{g}/\surd $ Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

Abstract

This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout circuit architecture. A phase lock loop (PLL) with a hybrid and antinoise folding PFD is employed to sustain the oscillation of the MEMS oscillator, and the oscillation amplitude is set by an external reference. In addition, a sigma-delta frequency-to-digital converter is combined with the PLL to digitize the accelerometer’s frequency output for low power consumption. The MEMS transducer and the readout circuit are fabricated in an 80- $\mu \text{m}$ SOI and standard 0.35- $\mu \text{m}$ CMOS process, respectively. The SOA achieves 0.23- $\mu \text{g}$ bias instability and 1- $\mu \text{g}$ /Hz $^{1/2}$ acceleration noise density with a ±30 g full-scale, which are equivalent to 4-ppb relative instability and 17-ppb/Hz $^{1/2}$ relative acceleration noise density. It only consumes 2.7 mW under a 1.5 V supply.