CMOS Readout Circuit Research Articles

A CMOS Readout Circuit for Resistive Transducers Based on Algorithmic Resistance and Power Measurement

This paper reports a readout circuit capable of accurately measuring not only the resistance of a resistive transducer, but also the power dissipated in it, which is a critical parameter in thermal flow sensors or thermal-conductivity sensors. A front-end circuit, integrated in a standard CMOS technology, sets the voltage drop across the transducer, and senses the resulting current via an on-chip reference resistor. The voltages across the transducer and the reference resistor are digitized by a time-multiplexed high-resolution analog-to-digital converter (ADC) and post-processed to calculate resistance and power dissipation. To obtain accurate resistance and power readings, a voltage reference and a temperature-compensated reference resistor are required. An accurate voltage reference is constructed algorithmically, without relying on precision analog signal processing, by using the ADC to successively digitize the base–emitter voltages of an on-chip bipolar transistor biased at several different current levels, and then combining the results to obtain the equivalent of a precision curvature-corrected bandgap reference with a temperature coefficient of 18 ppm/°C, which is close to the state-of-the-art. We show that the same ADC readings can be used to determine die temperature, with an absolute inaccuracy of ±0.25 °C (5 samples, min–max) after a 1-point trim. This information is used to compensate for the temperature dependence of the on-chip polysilicon reference resistor, effectively providing a temperature-compensated resistance reference. With this approach, the resistance and power dissipation of a 100 $\Omega $ transducer have been measured with an inaccuracy of less than $\pm 0.55~\Omega $ and ±0.8%, respectively, from −40 °C to 125 °C.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

Abstract. Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

A 0.23- $\mu \text{g}$ Bias Instability and 1- $\mu \text{g}/\surd $ Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL

This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout circuit architecture. A phase lock loop (PLL) with a hybrid and antinoise folding PFD is employed to sustain the oscillation of the MEMS oscillator, and the oscillation amplitude is set by an external reference. In addition, a sigma-delta frequency-to-digital converter is combined with the PLL to digitize the accelerometer’s frequency output for low power consumption. The MEMS transducer and the readout circuit are fabricated in an 80- $\mu \text{m}$ SOI and standard 0.35- $\mu \text{m}$ CMOS process, respectively. The SOA achieves 0.23- $\mu \text{g}$ bias instability and 1- $\mu \text{g}$ /Hz $^{1/2}$ acceleration noise density with a ±30 g full-scale, which are equivalent to 4-ppb relative instability and 17-ppb/Hz $^{1/2}$ relative acceleration noise density. It only consumes 2.7 mW under a 1.5 V supply.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

CMOS Pixel Spectroscopic Circuits for Cd(Zn)Te Gamma Ray Imagers

A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

TEC-Less ROIC With Self-Bias Equalization for Microbolometer FPA

This paper describes a new CMOS readout circuit, which makes the microbolometer focal plane array have low spatial noise over a wide operating temperature range without a thermoelectric cooler. The readout circuit corrects the nonuniformity of each microbolometer pixel by the proposed self-bias equalization technique. The proposed readout circuit adopting the self-bias equalization has a feedback loop that makes the readout circuit find the bias voltage for the correction of nonuniformity by itself. The proposed circuit was fabricated using a 0.35-μm standard CMOS process. The measured results of the fabricated chip show that the spatial noise is less than the allowed spatial noise for the equivalent temperature difference of 50 mK over a wide operating temperature range.

Three-Dimensional Integration of Fully Depleted Silicon-on-Insulator Transistor Substrates for CMOS Image Sensors Using Au/SiO2 Hybrid Bonding and XeF2 Etching

Wafer bonding is a promising technology to enhance the performance and functionality of integrated circuits including memory devices, and large improvements have been made also in CMOS image sensors. In previous work, direct SiO2-SiO2 bonding and adhesive bonding techniques were employed to develop CMOS image sensors of a back-illumination type [1,2]. For cellular phone cameras, for instance, wafer bonding of an imaging pixel substrate and a logic circuit substrate was demonstrated to considerably reduce the chip size [3]. Cu-Cu bonding was reported to bond the III-V compound infrared detector array and the CMOS readout circuit, thereby reducing power consumption [4]. Wafer bonding is also expected to overcome the limitations of the conventional CMOS image sensors, such as dynamic range and signal processing capability [5,6].We have investigated an image sensor for future TV broadcast equipment, where pixel-parallel signal processing is needed. As shown in Fig. 1, three-dimensional (3D) device containing functional layers is made up of components such as photodiodes and signal processors through the pixel-wise vertical interconnections [7-9]. The signal from each photodiode is processed by the analog-to-digital converters within the pixel and read out in parallel. This new architecture allows a significantly large number of scanning lines than the conventional planar image sensors would do by the column-parallel signal processing architecture.To implement the structure of the image sensor, we developed a fabrication process for 3D integration of fully depleted silicon-on-insulator (FDSOI) transistor substrates by Au/SiO2 hybrid bonding and XeF2 etching [2,8]. Figure 2 shows a test chip that was experimentally constructed to demonstrate the effectiveness of this approach. The chip consists of a back-illuminated photodiode layer (upper substrate) and a signal processor layer (bottom substrate).Figure 3 illustrates the chip fabrication process. (a) FETs were first formed on FDSOI substrates. (b) Via holes were produced in the intermediate SiO2 layer by dry etching. (c) A Ti seed layer was deposited by sputtering and a Au film was formed by electroplating. (d) A Au/SiO2 hybrid surface was formed by chemical mechanical polishing (CMP), and the corresponding atomic force microscopy (AFM) image is shown in Fig. 4. (e) The hybrid surface was treated sequentially with Ar and O2 plasma, and the substrates were cooled to 15 °C to promote the absorption of water molecules on their surface. (f) The substrates were directly bonded using a force of 2000 N for 60 min at 200 °C and 1 Pa (Fig. 5(a)). (g) The Si handle layer of the upper substrate was removed to allow the light transmission to the photodiode. The handle layer was first thinned to 40 µm (Fig. 5(b)). (h) The remaining Si was removed by 75 cycles of XeF2 etching at 400 Pa for 30 s. Since the buried SiO2 acted as a natural etch stop, a completely smooth back surface could be obtained, as shown in Fig. 5(c). Figure 6 shows a cross-sectional scanning electron microscopy (SEM) image of the fabricated chip. Following the removal of the Si handle layer, the remaining thickness of the upper substrate was 6.5 µm. The alignment error was determined to be less than 3 µm and no interfacial voids were identified. From these results, it was concluded that a 3D test chip was successfully developed using the proposed method. This process is promising to stack more than 3 layers of substrate by repetition and to form additional backside electrodes [9].In conclusion, an experimental test chip was successfully fabricated using the Au/SiO2 hybrid bonding and the XeF2 etching to demonstrate the 3D integration of image sensor. The results clearly indicate the feasibility of fabrication method toward image sensors.

Si PIN Radiation Sensor with CMOS Readout Circuit

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-<TEX>${\mu}m$</TEX>-thick 4-inch n+ Si (111) wafer containing a <TEX>$2-k{\Omega}{\cdot}cm$</TEX> n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

MEMS 가속도센서를 위한 CMOS Readout 회로

본 논문에서는 MEMS(Micro Electro Mechanical System) 가속도센서를 위한 CMOS readout 회로를 설계하였다. 설계된 CMOS readout 회로는 MEMS 가속도 센서, 커패시턴스-전압 변환기(CVC), 그리고 2차 스위치드 커패시터 <TEX>${\Sigma}{\Delta}$</TEX> 변조기로 구성된다. 이들 회로에는 저주파 잡음과 오프셋을 감소시키기 위한 correlated-double-sampling(CDS)와 chopper-stabilization(CHS) 기법이 적용되었다. 설계 결과 CVC는 150mV/g의 민감도와 0.15%의 비선형성을 갖는다. 설계된 <TEX>${\Sigma}{\Delta}$</TEX> 변조기는 입력전압 진폭이 100mV가 증가할 때, 출력의 듀티 싸이클은 10%씩 증가하며, 0.45%의 비선형성을 갖는다. 전체 회로의 민감도는 150mV/g이며, 전력소모는 5.6mW이다. 제안된 회로는 CMOS 0.35um 공정을 이용하여 설계하였고, 공급 전압은 3.3V이며, 동작 주파수는 2MHz이다. 설계된 칩의 크기는 PAD를 포함하여 <TEX>$0.96mm{\times}0.85mm$</TEX>이다. This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor <TEX>${\Sigma}{\Delta}$</TEX> modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and <TEX>${\Sigma}{\Delta}$</TEX> modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed <TEX>${\Sigma}{\Delta}$</TEX> modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is <TEX>$0.96mm{\times}0.85mm$</TEX>.

CMOS Readout Circuit Integrated with Ionizing Radiation Detectors

Abstract This paper describes the work performed in ITE on integration in one CMOS chip the ionizing radiation detectors with dedicated readout electronics. At the beginning, some realizations of silicon detectors of ionizing radiation are presented together with most important issues related to these devices. Next, two developed test structures for readout electronics are discussed in detail together with main features of non-typical silicon process deployed.

Design of Readout Circuit for Pyroelectric Detector Based on Novel Pyroelectric Materials

Recently, scientists discovered that relaxor-based ferroelectric single crystals, such as (1-x)Pb(Mg1/3Nb2/3)O3 -xPbTiO3 (PMN-xPT, or PMNT) single crystals, exhibit extra-high pyroelectric responses. They are promising candidates for optical power detectors in broad bandwidth at ultraviolet, visible and infrared wavelength.To fabricate high performance infrared detectors with relaxor-based single crystals, the related readout circuit was investigated to increase signal-to-noise ratio, and 8×1 CMOS readout circuit is fabricated to gain very weak current, which provides a solution for uncooled large focal plane arrays devices based on relaxor-based single crystals.

Signal readout for pyroelectric detector based on relaxor ferroelectric single crystals

AbstractRelaxor‐based ferroelectric single crystals, such as (1 − x)Pb(Mg1/3Nb2/3)O3xPbTiO3 (PMNxPT, or PMNT) single crystals, exhibit large pyroelectric response, low thermal diffusivity, and high temperature stability. To fabricate high performance infrared detectors with relaxor‐based single crystals, the related readout circuit was investigated to increase signal‐to‐noise ratio, and 8 × 1 CMOS readout circuit is fabricated to gain very weak current, which provides a solution for uncooled large focal plane arrays devices based on relaxor‐based single crystals.

Design of a Smart CMOS Readout Circuit for Panoramic X-Ray Time Delay and Integration Arrays

This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6µm standard CMOS process for a 150×64 CdTe X-ray detector array. The readout circuit was found to effectively increase the charge storage capacity up to 1.6×108 electrons, providing an improved SNR by a factor of approximately 8. The measured equivalent noise charge resulting from the readout circuit was 1.68×104 electrons, a negligible value compared to the shot noise from the detector.

An integrated readout circuit for personal dosimetry with phase-shift compensation technique to improve stability

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35μm CMOS technology. It occupies an area of 2.113×0.81mm2. Measurement results show that the proposed channel can process up to 1MHz counting rate and provide a conversion gain of about 170mV/fC at a power dissipation of 330μW with a 3.3V power supply. Ac-coupled to a silicon PIN detector, it successfully detects β-rays.

Current mode read-out circuit for InGaAs photodiode applications

Infrared focal plane arrays have many military, industrial, medical, and scientific applications that require high-resolution and high-performance read-out electronics. In applications involving InGaAs sensor arrays, data read-out can be carried out by circuits implemented with 0.35μm CMOS technology. In this paper we propose a dynamically regulated cascode current mirror for pixel read-out. From simulation results, we expect this circuit to achieve a better trade-off between silicon area, signal-to-noise ratio, and output dynamic range than the trade-off that is currently achieved by current mode CMOS read-out circuits.

상보형 신호경로 방식의 CMOS 이미지 센서 픽셀의 하드웨어 구현

In this paper, an analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure consists of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Proposed CMOS image sensors pixel has been fabricated using 0.5 standard CMOS process. Measured results show that the output signal range is from 0.8 V to 3.8 V. This output signal range increased 125 % compared to conventional 3TR pixel in the condition of 5 V power supply.

Noise and mismatch optimization for capacitive MEMS readout

This paper presents a high precision CMOS readout circuit for a capacitive MEMS gyroscope. A continuous time topology is employed as well as the chopper noise cancelling technique. A detailed analysis of the noise and mismatch of the capacitive readout circuit is given. The analysis and measurement results have shown that thermal noise dominates in the proposed circuit, and several approaches should be used for both noise and mismatch optimization. The circuit chip operates under a single 5 V supply, and has a measured capacitance resolution of 0.2 aF/√Hz. With such a readout circuit, the gyroscope can accurately measure the angular rate with a sensitivity of 15.3 mV/°/s.

New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications

A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm × 15 μm area and consumes less than 0.4 mW power. Charge storage capacity is 3 × 108 electrons. The function and performance of the proposed readout circuit have been verified by experimental results.

APPLICATION OF ELECTROLESS Ni PLATING IN INFRARED FPA FABRICATION

Electroless nickel plating(ENP) is introduced to realize interconnection for a photosensitive array and CMOS read-out circuit(ROIC) in uncooled infrared focal plane array(UIRFPA) fabrication process.It has advantages of selective deposition and no requirement for external current source supply.The effective interconnection pencent can be over 85% by using this technology for 32×32 UIRFPA fabrication process.The method is certified as a simple,low cost and reliable method for interconnection between IRFPA and ROIC.

Radiation Effects in InGaAs and Microbolometer Infrared Sensor Arrays for Space Applications

Cobalt60, 60 MeV proton and heavy ion tests have been performed on InGaAs and amorphous silicon microbolometer arrays with CMOS readout circuits. The readout circuits showed latch-up at threshold LETs~14 MeV/mg/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , but the total dose and displacement damage effects were negligible for low earth orbit conditions. Effects in a microbolometer array tested, for use in Mercury orbit, to 100 krd(Si) and 3.2 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> 60 MeV p/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> showed acceptable performance, though there was a significant increase in power consumption for the CMOS readout circuit when biased during cobalt60 irradiation.