CMOS Process Research Articles

23.5–27.5 GHz Band Doherty Power Amplifier Integrated Circuit Using 28 nm Bulk CMOS Process Based on Dynamic Power Dividing Network

This paper presents a Doherty power amplifier (DPA) integrated circuit (IC) designed to have enhanced gain, efficiency, and AM-AM characteristics through a dynamic power dividing technique, which can control the power dividing ratio according to the input power. Since this multi-purpose dynamic power dividing network also provides the phase offset and impedance matching at the interstage network needed for appropriate DPA operation, the active IC area could be reduced. To verify the proposed technique and its analysis, the DPA was implemented with a 28 nm bulk CMOS process for the fifth-generation (5G) new radio (NR) millimeter-wave frequency band of 23.5–27.5 GHz. The measured results showed a gain of 20.3–21.9 dB, saturated output power of 14.0–15.2 dBm, power added efficiency (PAE) of 22.8–26.7% at the peak power, and PAE of 14.6–17.6% at the 6 dB output power back-off (OBO).

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

Dual-Band Low-Noise Amplifier for GNSS Applications

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively.

Device to circuit level implementation of JL-NSFET for DC/analog/RF applications at sub-5nm technology node: Design optimization and temperature analysis

Abstract ABSTRACT: This manuscript introduces, for the first time, a novel approach that incorporates a comprehensive analysis of sheet variations (1-5) and every individual sheet wise temperature variations, and as well as an investigation of various GS high-k gate dielectrics in Junction-less (JL) Nanosheet FET (JL-NSFET). The study starting from device level (Digital/Analog/Radio Frequency) to circuit (CMOS Inverter and ring oscillator) as a whole package is investigated through well calibrated TCAD simulation and the results portrayed. NSFETs are the ultimate choice for integrated circuits (ICs) at sub-5nm technology node. The notion of this paper is to design and optimization of NSFET with GS high-k gate dielectrics (Al2O3, HfO2, ZrO2 and TiO2) Initially. The switching/analog and RF metric revels that HfO2 is superior in terms SS, switching applications and more compactable with CMOS process. Further, adding number of sheets and temperature variation has been done later. As number of sheets increases, the effective channel width increases, electric field distribution takes place evenly and enhanced gate control owing to improved I_ON, I_ON/I_OFF ratio, SS and DIBL. However, increasing the number of vertical channel layers (sheets) more than 2 results into diminished analog/RF performance of JL-NSFET owing to increased parasitic capacitances. Further, the impact of temperature variations (250K to 450K) studied for different sheet variations (1 to 5) and noticed that analog/RF such as gm, gds, fT, TFP and GTFP are enhanced by 40.82%, 28.76%, 40.69%, 64.62% and 70.59%, respectively at lower temperature (250K). Furthermore, as the circuit level implementation CMOS inverter and 5-stage RO are examined for sheets increase, delay and EDP increases. For a CMOS inverter the NMH (0.295V) and NML (0.280V) are better at 2 sheets with a highest gain of 9.38 V/V. Hence, it is advised to use two or three sheets-based JL-NSFETs for high-performance and lower-power analog/RF applications.

A Direct Conversion Frontend With Bandwidth Extension and Linearity Enhancement for 5G Receivers

ABSTRACTIn this paper, a new frontend for 5G receivers is proposed. In the presented work, a new bandwidth enhancement technique for low‐noise transconductance amplifiers and for wireless frontends has been proposed. The proposed frontend achieves low noise figure (NF) by using a noise cancelation scheme in the newly proposed LNTA. The linearity of the frontend is also improved by increasing the DC gain and the bandwidth of the opamp used in the transimpedance amplifier and by exploiting a linearity improvement method for the LNTA. The frontend has been implemented in a standard 0.18 μm CMOS process. The post‐layout simulation results prove the gain of 38 dB with less than 3 dB deviation in the pass‐band over a 6.5 GHz bandwidth. The results also show that NF is less than 8 dB, the worst‐case IIP3 is −2 dBm, the maximum S11 is equal to −9.5 dB while the frontend consumes 9.95 mW DC power from a single 1.8‐V supply, and the occupied area is 0.813 mm2.

Research on high dynamic pixel structure based on adaptive integral capacitor

Infrared image sensing technology has attracted wide attention due to its advantages such as being unaffected by the environment, good target recognition, and strong anti-interference ability. However, with the improvement of the integration of infrared focal planes, the constraints between the dynamic range, noise, and full-shade of the optoelectronic system are particularly prominent. Therefore, in order to solve the contradiction between noise in weak light and full-shade capacity in strong light, in a 5 T infrared pixel circuit, the relationship between the capacitance value and voltage of the inverted MOS capacitor in a specific voltage range is used to make the integral capacitance of the infrared image sensor automatically change from 6.5 fF to 37.5 fF. A high dynamic pixel structure based on adaptive integral capacitance is proposed. Based on 55 nm CMOS process technology, 12288 × 12288its performance parameters are studied in a pixel-scale infrared sensor. The research results show that 5.5m × 5.5mthe small-size pixel has a large full-shade capacity of 1.31 Me- and a variable conversion gain, a noise of less than 0.43 e, and a dynamic range of more than 130 dB.

Ultra-Low Dark Count Rate SPAD Fully Integrated in a 180 nm High-Voltage CMOS Process

Ultra-Low Dark Count Rate SPAD Fully Integrated in a 180 nm High-Voltage CMOS Process

Single-Input Multiple-Output (SIMO) Cascode Low-Noise Amplifier with Switchable Degeneration Inductor for Carrier Aggregation.

This paper presents a single-input multiple-output (SIMO) cascode low-noise amplifier with inductive degeneration for inter- and intra-band carrier aggregation. The proposed low-noise amplifier has two output ports for flexible operation in carrier aggregation combinations for band 30 and band 7. However, during inter- and intra-band operation, gain variation occurs depending on the output mode. To compensate for this, a switching circuit is proposed to adjust the degeneration inductor, optimizing gain performance for both modes. The switching operation can minimize the control for the dynamic range in the receiver system to support carrier aggregation. The designed low-noise amplifier was fabricated using a 65 nm CMOS process, occupying an area of 2.1 mm2. In inter-band operation, the small-signal gain was measured by 18.9 dB for band 30 and 18.6 dB for band 7, with the noise figures of 1.03 dB and 1.07 dB, respectively. For intra-band operation, the small-signal gain was 17.3 dB and 17.2 dB, with the noise figures of 1.3 dB and 1.41 dB. The IIP3 values were measured by -7.6 dBm and -6.7 dBm for inter-band, and -6.3 dBm and -6.2 dBm for intra-band. Power consumption was 8.04 mW and 7.68 mW in inter-band, and 17.04 mW and 17.64 mW in intra-band depending on the output configuration.

Mixed‐mode SNN crossbar array with embedded dummy switch and mid‐node pre‐charge scheme

AbstractThis paper presents a membrane computation error‐minimized mixed‐mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid‐node pre‐charge scheme to construct a high‐precision current‐mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28‐nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 μW of power consumed. Moreover, the peak‐to‐peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample‐wise random variations.

An 11 nW, ＋0.34 °C/−0.38 °C inaccuracy self-biased CMOS temperature sensor at sub-thermal drain voltage

This paper presents a low-power, high-accuracy self-biased full CMOS temperature sensor based on sub-threshold currents at sub-thermal drain voltage. The sensor achieves high accuracy and minimal corner dependence by generating sub-threshold current ratios using NMOS transistors of different sizes operating at sub-thermal drain voltage. The proposed self-biased all-CMOS temperature sensing architecture enhances sensitivity by up to seven times and improves linearity. The overall stability under temperature fluctuations is significantly enhanced by utilizing a substrate diode structure that maintains constant current variation. Additionally, a high-threshold comparator with a fast response compresses the oscillator reset voltage difference, enabling ultra-low power operation. Timing logic control is employed to discard unstable cycle outputs, thereby reducing errors and achieving high-accuracy outputs. Operating at 1 V, the circuit consumes only 11 nW at 27 °C in a 180 nm CMOS process. It achieves a peak-to-peak inaccuracy of ＋0.34 °C/−0.38 °C from −10 to 100 °C after two-point calibration, with a resolution of 40 mK and a resolution FoM as low as 3.7 pJK2.

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm2. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm2, and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234 μW, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester.

Radiation Hardened Read-Stability and Speed Enhanced SRAM for Space Applications

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications.

A 132–170 GHz high-gain driving amplifier utilizing asymmetric broadside coupled line in 40-nm CMOS

This paper presents a driving amplifier (DA) utilizing the proposed asymmetric broadside coupled line. In contrast to conventional coupled line, the balun devised with proposed asymmetric coupled line and enhanced wideband balance compensation technique is utilized, thereby achieving wideband impedance matching and mitigating insertion loss. Additionally, the utilization of the lossy over-neutralization technique substantially enhances the power gain of amplifiers operating in the upper millimeter-wave band (150 GHz–300 GHz). The DA is fabricated utilizing a 40-nm CMOS process without aluminum layers. The fabricated amplifier demonstrates a compact total area of 0.135 mm2 (0.031 λ2), with a core area of 0.027 mm2 (0.0061 λ2). It achieves a high gain of 19.4 dB, high power of 11.05 dBm, and high power-added efficiency (PAE) of 11.05% at 160 GHz. Moreover, both the 3-dB power gain bandwidth and the 3-dB saturated power bandwidth extend from 132 GHz to 170 GHz, covering a bandwidth of 38 GHz. This configuration underscores the robust performance of the DA in the upper millimeter-wave band.

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.

4D-tracking with digital SiPMs

Silicon Photomultipliers (SiPMs) are the state-of-the-art technology in single-photon detection with solid-state detectors. Single Photon Avalanche Diodes (SPADs), the key element of SiPMs, can now be manufactured in CMOS processes, facilitating the integration of a SPAD array into custom monolithic ASICs. This allows implementing features such as signal digitization, masking, full hit-map readout, noise suppression, and photon counting in a monolithic CMOS chip. The complexity of the off-chip readout chain is thereby reduced.These new features allow new applications for digital SiPMs, such as 4D-tracking of charged particles, where spatial resolutions of the order of 10µm and timestamping with time resolutions of a few tens of ps are required.A prototype of a digital SiPM was designed at DESY using the LFoundry 150nm CMOS technology. Various studies were carried out in the laboratory and at the DESY II test-beam facility to evaluate the sensor performance in Minimum Ionizing Particles (MIPs) detection. The direct detection of charged particles was investigated for bare prototypes and assemblies coupling dSiPMs and thin LYSO crystals. Spatial resolution ∼20µm and a full-system time resolution of ∼50ps are measured using bare dSiPMs in direct MIP detection. Efficiency >99.5%, low noise rate and time resolution <1ns can be reached with the thin radiator coupling.

A low power low phase noise wide frequency range PLL

This paper presents a low-noise, low-power, wide output frequency range phase-locked loop (PLL) for WLAN/WiFi transceivers. By employing a dual-symmetric CMOS cross-coupled pair differential inductor voltage-controlled oscillator (VCO), the design achieves low phase noise. In addition, an improved phase frequency detector (PFD) and a programmable low-mismatch charge pump (CP) with feedback compensation bias control are used to mitigate bandwidth and noise variations caused by different reference frequencies. The improved charge pump PLL (CPPLL) is designed in 65 nm CMOS process, and the chip layout occupies an area of 0.28 mm2. Post-layout simulation results indicate that the PLL has a tuning range of 4.6 GHz to 6 GHz, a phase noise of 111.7 dBc/Hz at 1 MHz offset at 5 GHz, a total power consumption of 7.14 mW, and a lock time of about 9μs.

A 10 MHz‐BW 85 dB‐SNDR 4th‐order sturdy MASH 2‐0 noise shaping SAR ADC with 2nd‐order gain‐error‐shaping technique

AbstractThe multi‐stage noise shaping (MASH) ΣΔ ADC has a good potential to achieve high‐order noise shaping (NS) and high resolution. However, it suffers from quantization noise leakage caused by the mismatch between the analogue NS filter and the digital cancellation filter, which greatly degrades the ADC performance. The sturdy MASH topology of the ΣΔ ADC can solve the leakage issue, but it cannot be implemented using the NS SAR ADC due to structural limitations. This paper proposes a sturdy MASH 2‐0 NS SAR to solve the noise leakage issue. The 4th‐order NS is achieved by only using a 2‐0 topology, which is hardware efficient. Instead of eliminating the first‐stage quantization error, the proposed sturdy MASH 2‐0 NS SAR shapes it, achieving better robustness to PVT variables. Furthermore, owing to the first‐stage 2nd‐order NS capability, the impairments of the residue amplifier, including the gain error and nonlinearity, are 2nd‐order shaped. The proposed 4th‐order sturdy MASH 2‐0 NS SAR is implemented in a 28 nm CMOS process, which achieves a SNDR of 85.6 dB and a SFDR of 101.3 dB with 10 MHz BW at OSR of 10, resulting in a Schreier FoM of 178.8 dB/179.4 dB (in SNDR/DR) with power consumption of 4.8 mW.

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.