Abstract
AbstractThis paper presents a membrane computation error‐minimized mixed‐mode spiking neural network (SNN) crossbar array. Our approach involves implementing an embedded dummy switch scheme and a mid‐node pre‐charge scheme to construct a high‐precision current‐mode synapse. We effectively suppressed charge sharing between membrane capacitors and the parasitic capacitance of synapses that results in membrane computation error. A 400 × 20 SNN crossbar prototype chip is fabricated via a 28‐nm FDSOI CMOS process, and 20 MNIST patterns with their sizes reduced to 20 × 20 pixels are successfully recognized under 411 μW of power consumed. Moreover, the peak‐to‐peak deviation of the normalized output spike count measured from the 21 fabricated SNN prototype chips is within 16.5% from the ideal value, including sample‐wise random variations.
Published Version
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