CMOS Process Technology Research Articles

A W-Band 2 × 2 Rectenna Array With On-Chip CMOS Switching Rectifier and On-PCB Tapered Slot Antenna for Wireless Power Transfer

This article presents a W-band rectenna unit that incorporates a novel CMOS switching rectifier and a print tapered slot antenna. The operation principle of the switching rectifier is analyzed. The proposed rectifier topology shows improved reliability, and it utilizes the body-diode effect (BDE) to improve power conversion efficiency (PCE). Besides, a high-gain W-band antipodal linearly tapered slot antenna is implemented on PCB to improve the overall efficiency. In order to demonstrate the utility of the proposed rectenna unit for large-scale rectenna array, a 1 × 2 (parallel) and 2 × 2 (series-parallel) rectenna arrays in 40-nm bulk CMOS technology and PCB process have been implemented. The switching rectifier achieves a peak PCE of 45.8% at 94GHz with improved reliability. Occupying only 0.0756 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the overall PCEs of the rectenna unit and the 2 × 2 rectenna array are 25% and 23%, delivering 5.6and 20-mW output dc power, respectively, at 90-mW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> incident power density. The proposed rectifier and rectenna array achieve the highest PCE among recently reported W-band rectifiers and rectenna arrays with different technologies.

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.

Asynchronous early output majority voter and a relative-timed asynchronous TMR implementation

This article presents a new asynchronous early output 3-input majority voter that is used to realize a high-speed, low power and less area occupying relative-timed asynchronous TMR implementation. The proposed majority voter is used to realize an asynchronous TMR implementation and it is compared with asynchronous TMR implementations realized using other asynchronous majority voters. The dual-rail code was used for data encoding and two kinds of four-phase handshaking were used for data communication. Compared to the existing implementations, we find that the proposed asynchronous majority voter leads to an efficient TMR implementation by simultaneously reducing the cycle time, silicon area, and average power dissipation by 25.1%, 7.5% and 7.8% respectively, on average. The implementations used a 32/28 nm CMOS process technology.

Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

On-chip ultra low power optical wake-up receiver for wireless sensor nodes targeting structural health monitoring

Wireless sensor network (WSN) consists of distributed nodes deployed for monitoring the physical conditions and organizing collected data at the central control unit. Power consumption is the challenges in WSN as the network consists of wireless sensor nodes becomes denser. By utilizing WSN and visible light technology, a simple health monitoring system design can be approached that are smaller in size, faster and lower power consumption. This work focuses on design a low power optical wake-up receiver to reduce the energy consumption of each node in WSN. A wake-up receiver is designed to be always-on for detecting incoming signal and switches on the stand by protocol controller and WSN network for data transmission process. The characteristic of optical transmission and functional circuit of a wake-up receiver has been investigated. A low power optical wake-up receiver has been designed in 180nm Silterra CMOS process technology. The proposed wake-up receiver consumes only 443pW in standby mode and 1.89nW in active mode. The proposed optical wake-up receiver drastically reduces the power consumption by more than one third compared to other wake-up receivers which could be a milestone in the medical field if successfully conducted.

Floating memristor and inverse memristor emulation configurations with electronic/resistance controllability

This study presents two configurations to realise the behaviour of a floating memristor and an inverse memristor. The modified version of VDCC (voltage differencing current conveyor) termed as MVDCC (modified VDCC) is used to develop the presented emulators. The floating memristor emulator uses a single MVDCC and two grounded passive elements while the configuration of floating inverse memristor emulator is based on two MVDCCs, two grounded resistances and single grounded capacitance. The behaviour of both the circuits can be controlled through applied bias voltage as well as the employed grounded resistances. Both the presented circuits do not employ any external analogue multiplier circuit/IC, which can be considered as the most notable feature of these circuits. This study also describes the mathematical properties of memristor and inverse memristor taking both symmetrical and non-symmetrical models into account. PSPICE simulation tool is used to verify the working of realised emulation circuits using 0.18 μm CMOS process technology. The implementations of realised emulators, employing commercial ICs like AD844, CA3080 and LM13700, have also been presented and validated.

Energy-Efficient Implementation of Carrier Phase Recovery for Higher-Order Modulation Formats

We introduce circuit implementations of one- and two-stage carrier phase recovery (CPR) for 256QAM coherent optical receivers. We describe in detail the optimizations of algorithms, such as modified Viterbi-Viterbi (mVV), blind phase search (BPS), and principal component-based phase estimation (PCPE), that are required to develop energy-efficient CPR circuits and show how design parameter settings and limited fixed-point resolution affect the SNR penalty. 30-GBaud CPR circuit netlists synthesized in a 22-nm CMOS process technology allow us to study trade-offs between energy per bit and SNR penalty. We show that it is possible to reach an energy dissipation of around 1 pJ/bit at an SNR penalty of 0.6 dB for two-stage PCPE+BPS and mVV+BPS implementations, and that PCPE+BPS is the preferred choice thanks to its smaller area.

New MGDI-based full adder cells for energy-efficient applications

ABSTRACT In this paper, we present two new logic schemes to implement full adder cell using XOR-XNOR and NOR gates. Gate diffusion input (GDI) and modified GDI (MGDI) cells help to design low power circuits using less number of transistors. In this work, we design two new NOR gates based on MGDI cell. Then, using one of them and MGDI XOR-XNOR gates, two low-power and energy-efficient full adders which also meet full-swing property are proposed. The performance of our new full adders is evaluated and compared with some of the familiar full adders. Post-Layout simulations using Cadence Virtuoso tools in TSMC 0.18 μm CMOS process technology are carried out and the results show almost 24%–56% (22%–55%) and 36%–66% (28%–62%) improvements in the features power consumption and power-delay product (PDP), respectively. Also, full-swing property of our new adders are proved when they are subjected to all possible input combinations and transitions.

On-Chip Implementable Autocalibration of Sensor Offset for Differential Capacitive Sensor Interfaces

In this article, we propose an autocalibration method to cancel out the mismatch between the sensing capacitors in differential capacitive sensors. The proposed autocalibration logic is implemented with the help of a field-programmable gate array (FPGA) and a few discrete components that can be integrated fully on-chip. The calibration logic is based on successive approximation principle and integrated with a low offset capacitive sensor interfacing application-specific integrated circuit (ASIC). The interfacing ASIC employs switched-capacitor-based time-multiplexed chopper modulation and demodulation principles to reduce the low-frequency noise and offset from the circuit components. In the proposed design, an array of programmable on-chip capacitors is included within the ASIC for automatic calibration. It also includes a 16-bit serial-input parallel-output (SIPO) shift register for calibration and to configure the control signals required for other blocks in the ASIC. The interfacing ASIC is designed and fabricated in the United Microelectronics Corporation (UMC) 180-nm CMOS process technology. The ASIC along with the autocalibration logic is integrated with a MEMS-based capacitive acceleration sensor, and the measurement results are presented. The measurement results show that the proposed scheme is able to compensate for the mismatch between the sensing capacitors, keeping zero offset less than 2 mV, and provides a sensitivity of 200 mV/g with 300- $\mu \text{g}/\sqrt {Hz} $ noise floor.

Design of a SIW on-chip antenna using 0.18-μm CMOS process technology at 0.4 THz

A 0.4-THz on-chip antenna (OCA) is configured with high radiation efficiency and high gain, utilizing standard CMOS process technology. In this design, the back cavity is formed by connecting a top and bottom metal layer, which is connected through the vias, named substrate-integrated-waveguide (SIW). This back cavity finds to suppress the surface wave and separates the radiation towards the low-resistive substrate. The slotted radiator is constructed on the top metal layer that leads to enhance the radiation performance in broadside direction. The projected antenna size of 490 × 450 μm2 and shows a 3-dB gain bandwidth of ∼ 39 %, a directivity of ∼7.02 dBi, a radiation efficiency of ∼ 87.9 % in the frequency range from 0.380 THz to 0.420 THz. This OCA is suitable for various THz applications in suggested band.

Design and Analysis of 2 GHz Low Noise Amplifier Layout in 0.13um RF CMOS

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (Cex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS . And also, this work has been implemented in a 0.13um RF CMOS technology process.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Single event transient study on PMOS-NMOS cross-coupled LC-VCO using PLL

ABSTRACT A theoretical analysis for single event transient phenomena in a cross-pair LC-VCO (Inductor Capacitor-VCO) is presented. The analytical model developed using unit step approximation for the dual double exponential SET current pulse closely captures the SET phenomenon in the LC resonant tank. Also, a model developed to capture the increase or decrease in the transconductance of the cross pair VCO in response to SET hit in the tail transistor and the transistor connected to the output of the VCO is presented. The developed model helps to capture the voltage and phase variation caused by the SET pulse more accurately in the oscillator. Further, the performance of LC-VCO under SET hit has been observed within PLL for different swing values. The simulation result shows that the recovery time and phase displacement produced by SET can be reduced by biasing the LC-VCO in the current limited regime and by having a large swing. The simulation results for cross-coupled LC-VCO are validated with 90 nm CMOS process technology.

DPL-based novel CMOS 1-Trit Ternary Full-Adder

ABSTRACT This paper presents a new high-speed, low-power, area-efficient 1-trit Ternary-Full-Adder (TFA) as a building block for wave-pipelined ternary-digital system design. Balanced input capacitance with structural symmetry makes Double Pass-transistor Logic (DPL) an ideal candidate for this, and is employed here hence. Design-strategy with working-principle is presented. The TFA is designed and optimised on normal-process-enhancement-type MOS devices that use BSIM4 model-parameters, on 1.0 V supply-rail at 27°C temperature. Simulations are carried out using Tanner EDA V.16. The ternary values ‘0’, ‘1’ and ‘2’ are coded with 0 V, 0.5 V and 1.0 V, respectively. The circuit is time-equalised through coarse and fine-tuning for all data paths from input-to-output to offer efficient wave-pipelining feature. The transient response from T-Spice simulation is validated for all test-patterns. Physical design of proposed TFA is completed using TSMC 65 nm Single-Poly-Double-Metal (SPDM) CMOS process-technology using Microwind3.1. After DRC, LVS and parasitic extraction, the post-layout simulation is done. PVT analysis with statistical PVT (Process-Voltage-Temperature) variation is used to find a worst-case speed-power response of the TFA. Propagation delay is examined for all test patterns and is found satisfactory ensuring effective wave-pipelining. Comparative study with recent candidate designs reveals nearly 21.43% PDP-reduction over the best reported.

A 3-D Simulation-Based Approach to Analyze Heavy Ions-Induced SET on Digital Circuits

Radiation-induced single-event transients (SETs) are the leading cause of mal-operations in CMOS nanometric integrated circuits. The increasing complexity of advanced CMOS digital circuits makes SET effects investigation a rising challenge. In this work, we propose a 3-D-oriented simulation approach able to model the passage of heavy ion particles through the physical structures of modern digital circuits implemented with ultrananometric manufacturing processes. The proposed approach is able to generate the transient voltage pulse in response to a heavy-ion track and identify the effects of the sensitive volume and contact structure. We present heavy-ion radiation test experiments performed on a 65-nm Flash-based CMOS technology process and, as proof-of-concept, we successfully compared the SET cross sections showing comparable results.

Barometric Pressure Sensor with Air Pocket Integrated with MOSFETs on the Same Substrate

In this paper, we propose a process to efficiently integrate barometric pressure sensors and MOSFETs on the same chip and show the measured results from these devices. The barometric sensor and MOSFETs are fabricated on the same Silicon substrate using CMOS process technology. The main process steps for the fabrication of the barometric sensor and MOSFETs are explained. Air pockets are connected around the barometric sensor and improve the sensitivity of the barometric sensor. The barometric sensor has a 0.5 μm thin diaphragm, which can reduce the size of the barometric sensor. The operating characteristics of the barometric sensor and the MOSFETs fabricated on the same substrate are verified.

A New Low-Capacitance High-Voltage-Tolerant Protection Clamp for High-Speed Applications

A new low-capacitance clamp is introduced for high-voltage-tolerant and high-speed interface applications. An embedded stacking architecture is proposed to address latch-up-immune design requirements without degradation in the electrostatic discharge (ESD) stress-handling capability, leakage, or capacitance. Thanks to a parallel current conduction path activated during ESD stress, a state-of-the-art failure threshold current per unit area is obtained for high-voltage-tolerant interface applications in sub-28-nm CMOS process technologies. The device design concept introduced in this article facilitates the implementation of compact, high-performance interface applications, extended in general to protection clamp devices requiring a higher holding voltage.

Novel Memristor Emulators using Fully Balanced VDBA and Grounded Capacitor

In this paper, grounded and floating decremental/incremental memristor emulator circuits are realized using fully balanced voltage differencing buffered amplifier (FB-VDBA) and grounded capacitor. These proposed configurations are simpler in design as compared to most of the designs available in the literature. The pinched Hysteresis loops are maintained up to 1 MHz frequency. The decremental to incremental memristor emulator and vice versa can be easily attained by slightly modifying the circuits. Proposed designs of memristor emulator circuits are simulated using TSMC 0.18 µm CMOS process technology parameters of Mentor Graphics Eldo tool. The proposed decremental floating memristor emulator circuit has been embedded in the design of universal biquad filter to evaluate its performance.

Single event transient hardened delay cell for a differential ring VCO

This paper presents a new single event transient hardened complementary delay cell (SET-H CDC) for radiation environment. The performance of the proposed topology has been compared with the existing radiation-hardened delay cell topologies called wide tuning delay cell and complementary delay cell (CDC). A three-stage VCO has been designed with each of the delay cell topologies for low power consumption while maintaining maximum swing. The VCO is designed using 90 nm CMOS process technology work with 1 Volt DC supply operating at 2.6 GHz frequency. The proposed topology shows better single event tolerance and reduced Impulse Sensitivity Function (ISF) while maintaining a rail-rail swing over a wide frequency tuning range. The proposed topology achieves a 17% improvement in rms ISF compared to wide tuning delay cell and 1.2% improvement compared to CDC delay cell.

A Fast Transient Response Hybrid LDO With Highly Accurate DC Voltage Using Countable Bidirectional Binary Search and Soft Swap Switching

This brief proposes a fast transient response hybrid low dropout (LDO) regulator with highly accurate DC voltage for system-on-chip (SoC) applications. The proposed hybrid LDO, which consists of the analog and digital LDOs (ALDO and DLDO), and a hybrid controller, employs a hybrid algorithm in the hybrid controller to control the ALDO and DLDO so as to produce its accurately regulated output voltage. The proposed hybrid algorithm is realized with the countable bidirectional binary search (CBBS) and soft swap switching (SSS) through logic synthesis. The CBBS quickly determines the coarse-tuning current of the DLDO by controlling the number of turned-on switches in the DLDO, resulting in a fast transient response. In addition, the SSS precisely adjusts the fine-tuning current of the ALDO by controlling the moment when the ALDO is activated, resulting in a highly accurate DC voltage. The proposed hybrid LDO was fabricated using a 0.18-μm standard CMOS process technology. The measurement results show that the output of the hybrid LDO is regulated at 0.9 V when the input voltage ranges from 1.2 V to 1.8 V. In addition, the measured undershoot and overshoot voltages are 34 mV and 56 mV with the settling times of 68 ns and 344 ns, respectively, at a load current step of about 40 mA. Therefore, the proposed hybrid LDO is suitable for SoC applications requiring fast transient response and highly accurate DC voltage.