On-Chip Implementable Autocalibration of Sensor Offset for Differential Capacitive Sensor Interfaces

Abstract

In this article, we propose an autocalibration method to cancel out the mismatch between the sensing capacitors in differential capacitive sensors. The proposed autocalibration logic is implemented with the help of a field-programmable gate array (FPGA) and a few discrete components that can be integrated fully on-chip. The calibration logic is based on successive approximation principle and integrated with a low offset capacitive sensor interfacing application-specific integrated circuit (ASIC). The interfacing ASIC employs switched-capacitor-based time-multiplexed chopper modulation and demodulation principles to reduce the low-frequency noise and offset from the circuit components. In the proposed design, an array of programmable on-chip capacitors is included within the ASIC for automatic calibration. It also includes a 16-bit serial-input parallel-output (SIPO) shift register for calibration and to configure the control signals required for other blocks in the ASIC. The interfacing ASIC is designed and fabricated in the United Microelectronics Corporation (UMC) 180-nm CMOS process technology. The ASIC along with the autocalibration logic is integrated with a MEMS-based capacitive acceleration sensor, and the measurement results are presented. The measurement results show that the proposed scheme is able to compensate for the mismatch between the sensing capacitors, keeping zero offset less than 2 mV, and provides a sensitivity of 200 mV/g with 300- $\mu \text{g}/\sqrt {Hz} $ noise floor.