A New Low-Capacitance High-Voltage-Tolerant Protection Clamp for High-Speed Applications

Abstract

A new low-capacitance clamp is introduced for high-voltage-tolerant and high-speed interface applications. An embedded stacking architecture is proposed to address latch-up-immune design requirements without degradation in the electrostatic discharge (ESD) stress-handling capability, leakage, or capacitance. Thanks to a parallel current conduction path activated during ESD stress, a state-of-the-art failure threshold current per unit area is obtained for high-voltage-tolerant interface applications in sub-28-nm CMOS process technologies. The device design concept introduced in this article facilitates the implementation of compact, high-performance interface applications, extended in general to protection clamp devices requiring a higher holding voltage.