CMOS Process Technology Research Articles

A novel 5.1–7.1 GHz front-end power amplifier for wireless applications with [formula omitted] dB Error Vector Magnitude

A Power Amplifier (PA) is proposed for WiFi-6E applications, specifically designed to support WLAN 802.11ax standard to achieve significant linear power. The proposed PA is designed to operate in the entire 5 GHz and 6 GHz frequency bands. The design involves a two-stage configuration, initial stage adopts a linear driver, while the subsequent amplification stage is structured as a differential cascode. UMC 65 nm CMOS process technology is used to design a PA in commercial Cadence platform. The layout occupies core area of 0.24 mm2. Proposed PA delivers a power gain of 20 dB, Power Added Efficiency (PAE) of 19% and 1 dB compression point (P1dB) is of 24.5 dB is achieved for continuous wave (CW) signal. For the 802.11ax source, the recorded average power output (Pavg) is 17.1 dBm at an Error Vector Magnitude (EVM) ≤−35 dB, across the 5–7 GHz. The PA delivers Pavg of 10 dBm at worst corner case in PVT variation analysis. While the majority of recent works in WLAN PA confines the investigation to 5 GHz band, this paper broadens the scope by extending the study by up to 7.050 GHz in 6 GHz band. The incorporation of 6GHz band enables WiFi-6E to utilize up to 1,200 MHz of unencumbered spectrum, significantly enhancing the available bandwidth relative to earlier WiFi standards. The increased bandwidth facilitates high data rate applications, such as streaming and gaming.

Research on high dynamic pixel structure based on adaptive integral capacitor

Infrared image sensing technology has attracted wide attention due to its advantages such as being unaffected by the environment, good target recognition, and strong anti-interference ability. However, with the improvement of the integration of infrared focal planes, the constraints between the dynamic range, noise, and full-shade of the optoelectronic system are particularly prominent. Therefore, in order to solve the contradiction between noise in weak light and full-shade capacity in strong light, in a 5 T infrared pixel circuit, the relationship between the capacitance value and voltage of the inverted MOS capacitor in a specific voltage range is used to make the integral capacitance of the infrared image sensor automatically change from 6.5 fF to 37.5 fF. A high dynamic pixel structure based on adaptive integral capacitance is proposed. Based on 55 nm CMOS process technology, 12288 × 12288its performance parameters are studied in a pixel-scale infrared sensor. The research results show that 5.5m × 5.5mthe small-size pixel has a large full-shade capacity of 1.31 Me- and a variable conversion gain, a noise of less than 0.43 e, and a dynamic range of more than 130 dB.

A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay

This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40[Formula: see text]nm CMOS technology process. The area of the proposed comparator is 28.025[Formula: see text][Formula: see text]m2. When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9[Formula: see text]V supply voltage, 25∘C, 1 GHz operational frequency, typical process corner (tt), and 1[Formula: see text]mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9[Formula: see text]ps from meta-stability analysis, energy per comparison of 0.175[Formula: see text]pJ/comparison and a kickback noise of 44.55 [Formula: see text]A. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.

A Novel Instruction Driven 1-D CNN Processor for ECG Classification.

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively.

Bias‐Switchable Dual‐Mode Organic Photodiodes Enabled by Manipulation of Interface Layers

AbstractBias‐switchable dual‐mode organic photodiodes (OPDs) that integrate photovoltaic and photomultiplication modes are recently developed and shown prospects in complex light‐intensity applications. Yet, the device physics that focuses on carrier dynamics is still a challenge and needs to be further explored. Herein, dual‐mode OPDs are developed through interface layer manipulation, that is, introducing cathode interface layers (typically, ZnxO:D149) with deep energy levels and abundant bulk defects and an anode interface layer of thermally‐evaporated ZnO (e‐ZnO) with a wide bandgap. Under reverse bias, ZnxO:D149 forms a barrier wall to effectively block external holes and maintain the photovoltaic mode of the OPDs. Under forward bias, the capturing effect of ZnxO:D149 and blocking effect of e‐ZnO help to reduce the dark current; when under illumination, defect traps capture photo‐generated holes, eliminating the barrier traps and promoting unobstructed injection of external carriers to achieve photomultiplication effect. The typical device delivers high specific detectivity (>1012 Jones) and fast response (<40 µs), and exhibits disparate external quantum efficiency in two operating modes, showing promise for simultaneously detecting faint and strong light. This general strategy for preparing dual‐mode OPDs is compatible with CMOS processing technology and meets the miniaturization and integration requirements of next‐generation detection systems.

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Design and simulation of a nano biosensor based on amorphous indium gallium zinc oxide (a-IGZO) thin film transistor

In this study, a biosensor utilizing a dielectric-modulated amorphous indium gallium zinc oxide (a-IGZO) thin film transistor (TFT) is introduced. TFT biosensors have garnered significant attention due to their heightened sensitivity, scalable nature, low power consumption, rapid electrical detection capabilities, and cost-effective means of mass production. By embedding a nano-cavity within the gate insulator of the TFT, biomolecules can accumulate within. As each biomolecule possesses its own dielectric constant, it modulates the effective gate capacitance and, subsequently, changes the channel conductance. To assess the sensitivity of the biosensor, variation in saturation current after the absorption of biomolecules with respect to the drain current in the case of an air-filled cavity has been considered as a precise measure. The efficient operation of a biosensor is contingent upon the sensitivity being highly dependent on the dielectric constant of the biomolecules that are accumulated within the nano-cavity. Consequently, a comprehensive evaluation has been conducted to ascertain the impact of critical design parameters which have the potential to affect the sensitivity of the biosensor. Additionally, a statistical analysis based on coefficient of variation measure has been performed to evaluate the susceptibility of the biosensor’s sensitivity to variations in geometrical and physical design parameters. The utilization of label-free detection methodology in this device presents a notable advantage due to its compatibility with the fundamental CMOS processing technology and its cost-effective potential for macro production.

Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications

Approximate computing is an innovative design methodology to reduce the design complexity with an improvement in power efficiency, performance and area by compromising on the requirement of accuracy. In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation to produce the final products are proposed. Two approximate Probability Based Booth Encoders (PBBE-1 and PBBE-2) have been proposed and used in the Booth multipliers. Error parameters have been measured and compared with the existing approximate booth multipliers. Exact booth multiplier of novel design existing in the literature has also been implemented for comparison purpose. The proposed approximate multipliers are then used in applications like image multiplication and IIR bi-quad filtering to prove their performance. Simulation results prove that the proposed booth multipliers outperform the existing approximate booth multipliers in terms of power and area with better accuracy. Synthesis results prove that the proposed Multiplier 6 was found to be the most efficient with a 56 % power consumption improvement and a 47 % area improvement when compared to the exact multiplier. All the simulations are carried out using Cadence® Genus with 180 nm CMOS process technology.

Low-Power Analog Integrated Architecture of the Voting Classification Algorithm for Diabetes Disease Prediction.

A low-power (∼ 600nW), fully analog integrated architecture for a voting classification algorithm is introduced. It can effectively handle multiple-input features, maintaining exceptional levels of accuracy and with very low power consumption. The proposed architecture is based on a versatile Voting algorithm that selectively incorporates one of three key classification models: Bayes or Centroid, or, the Learning Vector Quantization model; all of which are implemented using Gaussian-likelihood and Euclidean distance function circuits, as well as a current comparison circuit. To evaluate the proposed architecture, a comprehensive comparison with popular analog classifiers is performed, using real-life diabetes dataset. All model architectures were trained using Python and compared with the software-based classifiers. The circuit implementations were performed using the TSMC 90 nm CMOS process technology and the Cadence IC Suite was utilized for the design, schematic and post-layout simulations. The proposed classifiers achieved sensitivity of ≥ 96.7% and specificity of ≥ 89.7%.

Bulk Cum QFG-Driven FVF Double Recycling Current Mirror Subthreshold OTA Based CCII+ Cell and Applications

This paper presents a low-voltage low-power second generation CCII+ cell using bulk-driven FVF class AB mode operated double recycling current mirror OTA. The OTA is used in the input core of CCII+ cell utilizes bulkcum Quasi Floating Gate (QFG)-based voltage to current converter and Partial Positive Feedback (PPF) to enhance the performance of the circuit. The circuit permits closely railto- rail input common mode range, high output current drive capability with low dual power supply of ± 0.25 V. This circuit produces low input referred noise of 1.65 μV/sqrt Hz, dissipates ultra-low power of 342 nW and is suitable for lowfrequency applications, such as bio-signal processing. Further, to validate this design, a MISO type voltage mode biquadratic filter and voltage mode two phase quadrature oscillator are currently being implemented using this CCII+ cells. The circuit is simulated in tanner EDA tools using 180 nm n-tub CMOS process technology with low bias current of 18 nA.

An Energy-Efficient ECG Processor with Ultra-Low-Parameter Multi-Stage Neural Network and Optimized Power-of-Two Quantization.

This work presents an energy-efficient ECG processor designed for Cardiac Arrhythmia Classification. The processor integrates a pre-processing and neural network accelerator, achieved through algorithm-hardware co-design to optimize hardware resources. We propose a lightweight two-stage neural network architecture, where the first stage includes discrete wavelet transformation and an ultra-low-parameter multilayer perceptron (MLP) network, and the second stage utilizes group convolution and channel shuffle. Both stages leverage neural networks for hardware resource reuse and feature a reconfigurable processing element array and memory blocks adapted to the proposed two-stage structure to efficiently handle various convolution and MLP layers operations in the two-stage network. Additionally, an optimized power-of-two (OPOT) quantization technique is proposed to enhance accuracy in low-bit quantization, and a multiplier-less processing element structure tailored for the OPOT weight quantization is introduced. The ECG processor was implemented on a 65nm CMOS process technology with 4KB of SRAM memory, achieving an energy consumption per interference of 0.15 uJ with a power supply of 1V, 64% energy saving compared to the recent state-of-the-art work. Under 4-bit weight precision, the 5-class ECG signal classification accuracy reached 98.59% on the MIT-BIH arrhythmia dataset.

78.8 pJ/b, 100 Mb/s Noncoherent IR-UWB Receiver for Multichannel Neurorecording Implants.

In this article, we present a novel approach for designing a low-power, low-area impulse radio ultra-wideband (IR-UWB) noncoherent receiver capable of achieving a data rate of 100 Mbps. Our proposed receiver demonstrates the ability to demodulate ON-OFF keying pulse streams across the entire lower frequency band defined by the Federal Communication Commission for UWB applications. The key components of the proposed receiver include a reconfigurable differential two-stage low-noise amplifier, a fully differential squarer, narrow-band interface rejection filters, and variable gain baseband amplifiers. These circuits work cohesively to ensure efficient signal reception and processing. To validate the performance of the proposed receiver, we implemented the design using TSMC 40-nm CMOS process technology. A short-range communication including a 1.5 cm tissue layer is tested utilizing a typical upconversion UWB transmitter fabricated in the same technology. Remarkably, the proposed receiver achieves a data rate of 100 Mbps with an impressively low energy efficiency of 78.8 pJ/b and occupies an area of 0.705 mm2. The compact size, remarkable energy efficiency, and high data rate capabilities of the proposed receiver meet the stringent requirements of neural recording implants.

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

Design and analysis of hybrid 10T adder for low power applications

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.

High Dynamic Pixel Structure Based on an Adaptive Integrating Capacitor.

Infrared image sensing technology has received widespread attention due to its advantages of not being affected by the environment, good target recognition, and high anti-interference ability. However, with the improvement of the integration of the infrared focal plane, the dynamic range of the photoelectric system is difficult to improve, that is, the restrictive trade-off between noise and full well capacity is particularly prominent. Since the capacitance of the inversion MOS capacitor changes with the gate-source voltage adaptively, the inversion MOS capacitor is used as the capacitor in the infrared pixel circuit, which can solve the contradiction between noise in low light and full well capacity in high light. To this end, a highly dynamic pixel structure based on adaptive capacitance is proposed, so that the capacitance of the infrared image sensor can automatically change from 6.5 fF to 37.5 fF as the light intensity increases. And based on 55 nm CMOS process technology, the performance parameters of an infrared image sensor with a 12,288 × 12,288 pixel array are studied. The research results show that a small-size pixel of 5.5 µm × 5.5 µm has a large full well capacity of 1.31 Me- and a variable conversion gain, with a noise of less than 0.43 e- and a dynamic range of more than 130 dB.

Performance Analysis of a Reconfigurable Mixer Using Particle Swarm Optimization

In this article, a novel 1.8-5 GHz downconversion mixer is presented. The mixer is designed and simulated using SiGe 8HP 130 nm CMOS process technology. The proposed mixer is implemented by incorporating a double-balanced configuration, active inductor, and current mirror techniques. For performance optimization of the proposed mixer, different algorithms such as the genetic algorithm (GA), inclined plane system optimization (IPO) algorithm, and particle swarm optimization (PSO) algorithm have been used. Compared to existing works, this design shows an enhanced conversion gain (CG), a third-order input intercept point (IIP3), and return loss ( S 11 ) at the expense of the noise figure (NF). Additionally, the design consumes low power and covers a small chip area compared to other state-of-the-art devices. PSO shows the most promising results when compared to other optimization algorithms’ results. According to the measurement results after PSO optimization, the mixer attains a maximum CG of 25 dB, an IIP3 of 4 dBm, and a NF of 5.2 dB at 5 GHz, while consuming only 15 mW of DC power. The mixer operates at 1.2 V and covers 0.8 mm2 die area.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency (Fosc) of an N-stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort (g) of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on Fosc of a given N-stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.

High-speed and energy-efficient asynchronous carry look-ahead adder.

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.

Realization of a new PMOS transistors based first-order delay equalizer suitable for communication networks

In this paper, a novel first-order delay equalizer based on a PMOS transistor is proposed which is highly suitable for the communication systems and networks. The core circuit consists of three unity-gain PMOS inverting amplifiers, one resistor and one capacitor. The newly proposed delay equalizer has ability to provide both inverting all pass and non-inverting all pass responses simultaneously from the same structure without restriction of any matching of passive elements to achieve desired performance. High input and low output impedances enable cascadability in the proposed circuit. The circuit's behaviour under loading effects and the effect of parasitic components are also examined in detail. To assess the applicability of the proposed structure, nth-order delay equalizer is also presented. The performance of the proposed work is validated through PSPICE simulations utilizing TSMC 0.18 μm level-7 CMOS technology process parameters, with voltage levels set at ±0.9 V. Furthermore, real-time post-layout verification is being carried out to ensure the confirmed performance.