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CMOS Phase-locked Loop Research Articles

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Overview
37 Articles

Published in last 50 years

Related Topics

  • All-digital Phase-locked Loop
  • All-digital Phase-locked Loop
  • Digital Phase-locked Loop
  • Digital Phase-locked Loop
  • Charge-pump Phase-locked Loop
  • Charge-pump Phase-locked Loop
  • Lock Loop
  • Lock Loop

Articles published on CMOS Phase-locked Loop

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Analysis of Single Event Transients in Arbitrary Waveforms Using Statistical Window Analysis

Window or taper functions are commonly used in data processing to detect transient events or for time-averaging of frequency spectra. A generalized window function is demonstrated using the Ionizing Radiation Effects Spectroscopy (IRES) technique to enhance the measurement of transient anomalies within arbitrary waveforms. The IRES filter is used to convolve time data with a sliding window consisting of a moment-generating function. The resulting time-dependent statistical moments can be used to eliminate any steady-state signatures, including noise, and extract transient behaviors. The IRES filter is used to analyze data from heavy-ion exposures of commercial off-the-shelf (COTS) operational amplifiers, laser-induced transients in CMOS phase-locked loops, and simulated transients in digital and analog circuits. The performance of the IRES filter in noisy environments shows that transients can be measured with higher fidelity than standard amplitude thresholding. This statistical window analysis technique may remove the need for complex triggering mechanisms on instrumentation and does not require <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a-priori</i> knowledge of transient characteristics. Potential applications of IRES include real-time measurement, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> data analysis, and machine learning.

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  • IEEE Transactions on Nuclear Science
  • Apr 1, 2023
  • J L Carpenter + 6
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A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

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  • Electronics
  • Jan 29, 2022
  • Xiaokang Niu + 5
Open Access
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Analysis of Single-Event Transients (SETs) Using Machine Learning (ML) and Ionizing Radiation Effects Spectroscopy (IRES)

A methodology for automating the identification of single-event transients (SETs) through ionizing radiation effects spectroscopy (IRES) and machine learning (ML) is provided. IRES enhances the identification of SETs through statistical analysis of waveform behavior, allowing for the capture of subtle circuit dynamics changes. Automated identification of SETs is facilitated by a k-nearest neighbors ( kNNs) ML algorithm with IRES data. One-hundred thousand waveforms were measured from CMOS phase-locked loop (PLL) circuits irradiated at the Naval Research Laboratory's two-photon absorption (TPA) laser facility. Known SET signatures were used to train various kNN models based on statistical features derived from several standard circuit metrics and eight moment-generating functions. Results show that SETs can be automatically identified by the kNN models, with several features resulting in greater than 98% correct identification of SETs. The tradeoffs in ML-based anomaly detection, based on the size of available training sets, choice in signal metric, and the number of included statistical moment-generating functions are discussed, along with opportunities for the future development of specific event-type classification, in situ measurement, and real-time classification of data.

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  • IEEE Transactions on Nuclear Science
  • Jan 13, 2021
  • T D Loveless + 4
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A Self‐Biased Low‐Jitter Process‐Insensitive Phase‐Locked Loop for 1.25Gb/s‐6.25Gb/s SerDes

The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A diffierential Charge pump (CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65nm and 55nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.

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  • Chinese Journal of Electronics
  • Sep 1, 2018
  • Hengzhou Yuan + 4
Open Access
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A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.

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  • AEU - International Journal of Electronics and Communications
  • Dec 24, 2017
  • Xiaoqiang Li + 5
Open Access
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UHF FRS 대역 CMOS PLL 주파수 합성기 설계

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a 0.35-μm standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator(3rd DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and −3.86 dBm radio-frequency output power. The phase noise of the output signal is −94.8 dBc/Hz, and the lock-in time is 300 μs.

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  • The Journal of Korean Institute of Electromagnetic Engineering and Science
  • Nov 1, 2017
  • Jeung-Jin Lee + 1
Open Access
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Low-power CMOS injection-locked and current-mode logic frequency dividers in a 50 GHz LC cross-coupled oscillator

This paper aims to design a low-power and high-frequency divider in an integrated CMOS phase-locked loop. The proposed frequency divider is a two-step divider composed of an injection-locked frequency divider (ILFD) and a current-mode logic (CML) frequency divider. The ILFD has a structure similar to an LC cross-coupled oscillator to adjust the frequency alignment between the oscillator and the ILFD. The LC cross-coupled oscillator operates at 50 GHz, and the ILFD is supposed to provide a divide-by-2 (/2) operation. The CML frequency divider, which is used as the second-stage divider, is applied with an inductive peaking structure for a wide band with low power consumption. The proposed two-step frequency divider is designed with a 0.18 µm CMOS process. By varying the numbers of the ILFD and the CML divider, the characteristics of power consumption are also studied. Post-layout simulation shows that the /2 ILFD and the /128 CML frequency divider operate at an input frequency of 50 GHz, with power consumption of 37.8 mW, and results indicate a low-power two-step divider at high frequency.

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  • Analog Integrated Circuits and Signal Processing
  • Jan 6, 2016
  • Jong-Phil Hong + 2
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A 40 GHz 65 nm CMOS Phase-Locked Loop With Optimized Shunt-Peaked Buffer

A 40 GHz phase-locked loop (PLL) with an optimized shunt-peaked buffer is realized in Global Foundries 65 nm CMOS technology. The shunt-peaked buffer placed in the loop eliminates the capacitive loading of the frequency divider and enhances the drive capability. Hence it is possible to use an inductorless frequency divider to reduce potential parasitics in the layout. Thanks to the simplified topology and enhanced output swing, the proposed PLL achieves a good balance among silicon area, output range and phase noise. Measurement shows that the PLL works properly from 39.5 to 41.7 GHz with a phase noise of -102.7, -112, -119 dBc/Hz at 1, 10, and 20 MHz offset from the carrier, respectively. It occupies a chip area of 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all the testing pads and consumes 87 mW from 1.5 V and 0.8 V supply voltage including the buffers.

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  • IEEE Microwave and Wireless Components Letters
  • Jan 1, 2015
  • Chen Feng + 3
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Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 μm CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.

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  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • Jan 1, 2015
  • Anders Jakobsson + 2
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Design and analysis of a K-band low-phase-noise phase-locked loop with subharmonically injection-locked technique.

In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree with the experimental results. Moreover, the phase noise of the PLL can be improved with the subharmonic injection. To achieve K-band operation with low dc power consumption, a divide-by-3 injection-locked frequency divider (ILFD) is used as a frequency prescaler. The measured phase noise of the PLL without injection is -110 dBc/Hz at 1 MHz offset at the operation frequency of 23.08 GHz. With the subharmonic injection, the measured phase noises at 1 MHz offset are -127, -127, and -119 dBc/Hz for the subharmonic injection number NINJ = 2, 3, and 4, respectively. Moreover, the performance of the proposed PLL with and without SIL technique can be compared with the reported advanced CMOS PLLs.

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  • IEEE transactions on ultrasonics, ferroelectrics, and frequency control
  • Dec 1, 2014
  • Yen-Liang Yeh + 1
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A low jitter PLL clock used for phase change memory

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

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  • Journal of Semiconductors
  • Feb 1, 2013
  • Xiao Hong + 4
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The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of the PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

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  • IEICE Transactions on Electronics
  • Jan 1, 2011
  • Zue-Der Huang + 1
Open Access
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Switchable PLL Frequency Synthesizer andHot Carrier Effects

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.

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  • Circuits and Systems
  • Jan 1, 2011
  • Yang Liu + 2
Open Access
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Design of High Gain, High Bandwidth Op-Amp for Reduction of Mismatch Currents in Charge Pump PLL in 180 nm CMOS Technology

The designing of charge pump with high gain OpAmp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENCE VIRTUOSO tool. This paper describes the design of high performance charge pump for GHz CMOS PLL targeting orthogonal frequency division multiplexing (OFDM) application. A high speed low power consumption Op-Amp with more than 500 MHz bandwidth has designed for increasing the speed of charge pump in Phase locked loop. Keywords—Charge pump (CP) Orthogonal frequency division multiplexing (OFDM),Phase locked loop (PLL), Phase frequency detector (PFD), Voltage controlled oscillator (VCO),

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  • Zenodo (CERN European Organization for Nuclear Research)
  • Dec 28, 2010
  • + 1
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A 0.5–1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixed-signal SoCs with a wide range of operating frequencies. The design proposes a multi-regulator PLL architecture, in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator, reducing the parasitic noise and spur coupling between different PLL building blocks. Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-fvco/1%-VDD. The design is fabricated in 0.13 μm 1.5/3.3 V CMOS technology. The in-band phase noise of −102 dBc/Hz at 1 MHz offset with a spur of less than −45 dBc is measured from 1.25 GHz carrier. The measured RMS jitter of the proposed PLL is 1.72 ps at a 1.25 GHz operating frequency. The total power consumption is 19 mW, and its active area is 0.19 mm2.

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  • Journal of Semiconductors
  • Sep 1, 2010
  • Jiao Yishu + 3
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A 1.5 V 7.656 GHz PLL with I/Q outputs for a UWB synthesizer

A fully integrated CMOS phase-locked loop (PLL) which can synthesize a quadrature output frequency of 7.656 GHz is presented. The proposed PLL can be employed as a building block for an MB-OFDM UWB frequency synthesizer. To achieve fast loop settling, integer- N architecture operating with 66 MHz reference frequency and wideband QVCO are implemented. I/Q carriers are generated by two bottom-series cross-coupled LC VCOs. Realized in 0.18 μm CMOS technology, this PLL consumes 16 mA current (including buffers) from a 1.5 V supply and the phase noise is −109.6 dBc/Hz at 1 MHz offset. The measured oscillation frequency shows that the QVCO has a range of 6.95 to 8.73 GHz. The core circuit occupies an area of 1 × 0.5 mm2.

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  • Journal of Semiconductors
  • Jun 1, 2010
  • Chen Pufeng + 2
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A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is − 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.

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  • International Journal of Electronics
  • Oct 1, 2009
  • Baoyong Chi + 4
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A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$\mu{\hbox{m}}$ CMOS for $V$-Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-mum CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are -85.2 and -90.9 dBc/Hz, respectively. The reference spur level of -40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band applications.

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  • IEEE Transactions on Microwave Theory and Techniques
  • Jul 1, 2009
  • Chung-Yu Wu + 2
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A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

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  • JSTS:Journal of Semiconductor Technology and Science
  • Mar 31, 2007
  • Kyung-Ki Kim + 1
Open Access
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A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

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  • Journal of Circuits, Systems and Computers
  • Oct 1, 2005
  • Robert C Chang + 2
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