A 0.5–1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

Abstract

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixed-signal SoCs with a wide range of operating frequencies. The design proposes a multi-regulator PLL architecture, in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator, reducing the parasitic noise and spur coupling between different PLL building blocks. Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-fvco/1%-VDD. The design is fabricated in 0.13 μm 1.5/3.3 V CMOS technology. The in-band phase noise of −102 dBc/Hz at 1 MHz offset with a spur of less than −45 dBc is measured from 1.25 GHz carrier. The measured RMS jitter of the proposed PLL is 1.72 ps at a 1.25 GHz operating frequency. The total power consumption is 19 mW, and its active area is 0.19 mm2.