Abstract
In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.
Highlights
Phase-locked loops (PLLs) have been widely used in high speed data communication systems
We propose a switchable PLL, which combines two relatively narrow bandwidth PLLs into a single chip and uses a frequency detector to decide which PLL to choose according to the reference frequency
Phase noise and jitter measured under hot carrier stress for both voltage-controlled oscillator (VCO) and PLL are reported in subsection 5.2
Summary
Phase-locked loops (PLLs) have been widely used in high speed data communication systems. The switchable PLL can work over a wide tuning range and at a high frequency. It achieves a short locking time without sacrificing the jitter and phase noise performance. More detailed studies on hot carrier effects in CMOS VCO which is one of the modules of the PLL have been conducted by Zhang and Srivastava [10,11]. Hot carrier effect has been considered and its effect on phase noise and jitter of the CMOS phase-locked loop integrated circuit has been studied
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