CMOS Injection-locked Frequency Divider Research Articles

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology

Based on a detailed analysis of harmonic generation in ring-based injection-locked frequency dividers (ILFDs), this article shows that concurrent injection signals can be generated in these stages by driving both tail and direct injectors with the same input signal. Based on this result, a novel ring-based divide-by-five ILFD is presented, where multi-injection is reinforced by a dual-path scheme, largely broadening the locking range with no penalty in power dissipation. The stage, implemented in a 28-nm CMOS process, operates over the 8-to-101.6-GHz frequency range achieving a >20% locking over the 13.6–69.1-GHz interval, with 5.6-mW maximum power consumption from a 0.9-V supply. The stage also achieves 101.6 GHz, the highest operating frequency among state-of-the-art CMOS ILFDs by five, with 2.6% locking range.

Design and analysis of 73-106 GHz CMOS injection-locked frequency divider

ABSTRACT A 73 ~ 106 GHz divide-by-2 injection-locked frequency-divider (ILFD2) using 90 nm CMOS technology is presented. To achieve a wide locking range, an optimal transistor width ratio of the injection transistor (or mixer) and cross-coupled transistors (CCT) is adopted. To enhance the operation frequency, distributed LC network is used as the load of the CCT. To enhance the input sensitivity, an input power matching network is included in the injection transistor. In addition, for further locking ranging enlargement, the inductive peaking and forward-body-bias techniques are used in the injection transistor for raising its quadrature output current (or conversion gain). The ILFD2 consumes 4.92 mW, and achieves an excellent phase noise of – 106.2 dBc/Hz (at 1 MHz offset from the output frequency of 50 GHz). The ILFD2 achieves a wide locking-range of 33 GHz (73–106 GHz (36.9%)), covering the 77 GHz automotive radar frequency band and the 94 GHz imaging radar frequency band. The ILFD2 can be operated at a low input power of – 60 dBm, one of the best input sensitivities ever reported for a W-band CMOS ILFD2. The core area of the ILFD2 is only 0.014 mm2.

Injection-Locked Frequency Divider With a Resistively Distributed Resonator for Wide-Locking-Range Performance

Distributed LC resonator and resistively distributed resonator belong to the same technique used to extend the locking range of injection-locked frequency divider (ILFD). ILFD using the former resonator often has one locking range, and extension of locking range is attributed to oscillation frequency increment. This paper measures and analyzes the input sensitivity of a CMOS ILFD with a resistively distributed resonator and with the divide-by-3 and divide-by-2 functions, and the input sensitivity shows a wide single-band locking range. The fabricated 0.18-μm CMOS ILFD is made of a pair of cross-coupled n-type transistors, two direct-injection MOSFETs, and a resistively dualresonance resonator. The wide single-band locking range of the designed ILFD is owing to the overlapped locking ranges, and it is verified by the smooth tuning range without forbidden region and nonoverlapped locking ranges measured on the same chip with the unbalanced injection structure. The frequency tuning is obtained with large tank resistance, which also reduces the frequency tuning hysteresis effect.

24-GHz Self-Injection-Locked Vital-Sign Radar Sensor With CMOS Injection-Locked Frequency Divider Based on Push–Push Oscillator Topology

In this letter, a 24-GHz CMOS injection-locked frequency divider (ILFD) based on the push–push oscillator topology is designed and fabricated. It is further treated as the kernel component of a self-injection-locked (SIL) radar sensor for noncontact vital-sign detection. The push–push topology is employed to double the oscillation frequency of the 12-GHz LC oscillator to provide the 24-GHz transmitting signal of the radar sensor, while the direct injection-locked configuration is used to divide the receiving 24-GHz injection signal by 2. Hence, the 12-GHz output of the ILFD can be connected with a differentiator-based envelope detector for vital-sign demodulation. By packaging the developed ILFD chip and connecting it with two antennas, a gain block, a differentiator-based envelope detector, and a 24-GHz SIL radar sensor can be built to detect the physiological chest movement of a human subject. The feasibility of developing a SIL radar sensor in the millimeter-wave range is also demonstrated.

Triple‐resonance RLC‐tank divide‐by‐2 injection‐locked frequency divider

Conventional CMOS injection-locked frequency dividers (ILFDs) were often designed with a single-resonance LC resonator and they have a single-band locking range. Wide-locking range in these ILFDs was obtained at the cost of lower output power. A triple-resonance (TR) resistor (R), inductor (L) and capacitor (C)-tank ILFD is presented to design a wide-locking range CMOS divide-by-2 circuit, which is based on a cross-coupled n-core MOS pair. The TR ILFD has three overlapped locking ranges seen as one-band locking range at high microwave injection power and it has large output power. At the core power consumption of 6.76 mW and at the microwave input power of 0 dBm, the divide-by-2 TR ILFD achieve a maximum locking range of 5.77 GHz (105.2%) from 2.6 to 8.37 GHz.

Enhanced locking range technique for frequency divider using dual‐resonance RLC resonator

An enhanced locking range technique for a CMOS injection-locked frequency divider (ILFD) is presented, which uses a cross-coupled oscillator with a dual-resonance RLC resonator. This ILFD has dual locking ranges at a fixed bias, and the resistor in the resonator is used to have overlapping dual locking ranges so that a single-band wide-locking range is obtained. At the incident power of 0 dBm, the locking range of the divide-by-2 ILFD is 6.7 GHz, from 3 to 9.7 GHz, and the locking range percentage is 105.51%.

A triple-band divide-by-2 CMOS injection-locked frequency divider

A triple-band and wide operation range divide-by-2 injection-locked frequency divider (ILFD) using a TSMC 0.18 μm 1P6 M CMOS technology is presented. The ÷2 ILFD circuit is realized with a cross-coupled n-core MOS LC-tank oscillator with a 6th order LC resonator constructed from three single-resonance parallel LC resonators. The core power consumption of the ILFD core is 11.6 mW at the supply voltage of 1 V. The free-running ILFD can operate at three frequency bands: 8.75, 5.79 and 3.7 GHz, and the ILFD operation range covers a high-band frequency range from 17.1 to 18.3 GHz, a middle-band from 10.1 to 12.7 GHz, and a low-band from 6.0 to 7.7 GHz. The band selection is obtained by tuning the varactor's control bias.

Wide‐locking range class‐C injection‐locked frequency divider

A novel wide-locking range divide-by-3 injection-locked frequency divider (ILFD) is designed and fabricated in a standard 0.18 μm CMOS process. The CMOS ILFD uses a class-C capacitive cross-coupled oscillator as the core. It has been found that the locking range of the ILFD is enhanced when the DC-gate bias is smaller than the drain bias in the cross-coupled pair. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. At the incident power of 0 dBm, the maximum locking range is 3.3 GHz (24.17%), from the incident frequency 12–15.3 GHz. At the incident power of 0 dBm, the operation range is 4.8 GHz (37.2%), from the incident frequency 10.5–15.3 GHz.

A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation

This paper proposes a simple and effective modification of the conventional divide-by-two injection locked frequency divider (ILFD) with direct-injection aimed at allowing both the divide-by-two and the divide-by-three modes of operation. The proposed circuit does not employ additional inductors as usual in divide-by-three ILFDs, but exploits the combined effect of two independent injection techniques. The resulting locking range for the divide-by-three mode is comparable in size to that for the divide-by-two. Thus, the proposed circuit can be an optimum alternative to existing dividers, due to the flexibility of two division ratios and due to the absence of additional inductors. An intuitive explanation of the locking mechanism underlying this ILFD and a quantitative analysis are provided, allowing one to predict the amplitude and phase of oscillation in the locked mode, as well as the locking range, with approximate closed-form expressions. Measurements on a circuit prototype and results from SPICE simulations demonstrate the effectiveness of the circuit and validate the theoretical model and the resulting formulas.

A 30GHz Wideband CMOS Injection-Locked Frequency Divider for 60GHz Transceiver

In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.

Modeling, Analysis, and Experimental Validation of Frequency Dividers with Direct Injection

An analytical model and a methodology are presented for the analysis of CMOS injection-locked frequency dividers with direct injection, which are used in modern wireless communication systems. The amplitude and phase of the oscillation in the synchronous operation mode, as well as the locking range, are found in explicit form. The width of the locking range is determined by the condition of the existence and stability of synchronous oscillations. The accuracy of the model and of the presented formulas is validated through a comparison with experimental results, which are in good agreement with the analytical ones.

G-Band Injection-Locked Frequency Dividers Using $\pi$-type LC Networks

Two high-frequency CMOS injection-locked frequency dividers (ILFDs) are realized by <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pi$</tex> </formula> -type LC networks. The frequency enhancement analysis and design considerations for the both ILFDs are given. The effects of vias and interconnections on the inductance and quality factor are also discussed. Both ILFDs have been fabricated in 65 nm CMOS process. The measured locking ranges of these two ILFDs are 182.7–185.7 GHz and 192.4–194.06 GHz, respectively.

A 0.35-μm CMOS frequency divider implemented with the waffle injection MOSFET

This letter proposes a CMOS injection-locked frequency divider (ILFD) fabricated in a 0.35-μm CMOS process.The ILFD circuit is realized with a cross-coupled CMOS LC-tank oscillator, and the external injection is carried out through the gate of a waffle MOSFET. The self-oscillating ILFD is injection-locked by second-/fourth-harmonic input to obtain the division order of two/four. Measurement results show that at the supply voltage of 0.9 V and at the incident power of 0 dBm, the locking range is from the incident frequency 4.25 to 6.35 GHz in the divide-by-2 mode. The locking range is from the incident frequency 10.75 to 11.25 GHz in the divide-by-4 mode. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26064

CMOS injection-locked frequency divider with two series-LC resonators

A fourth order resonator has been implemented to design an injection locked frequency divider (ILFD) implemented in a 0.18-μm CMOS process. The ILFD is realized with a cross-coupled nMOS LC-tank oscillator with a direct injection MOSFET and two series-LC resonators. At the supply voltage of 0.8 V, the low-band free-running tuning frequency is from 2.7 to 3.18 GHz. One excited high-band frequency band is measured, and the free-running tuning frequency is from 4.07 to 4.13 GHz. The divide-by-2 operational locking range is from 3.4 to 9.4 GHz, and the divide-by-4 operational locking range is from 10.5 (15.95) GHz to 13.6 (16.9) GHz for the low-(high)-frequency band. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:290–293, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25716

Excellent sensitivity 64.8‐GHz CMOS injection‐locked frequency divider with 10.2‐GHz locking range

AbstractA low‐power and wide‐locking‐range 64.8‐GHz injection‐locked frequency‐divider (ILFD) using standard 0.13 μm CMOS technology is reported. To enhance the locking range, a shunt inductor was introduced in the source node of the cross‐coupled transistor pair to maximize the equivalent load impedance of the tail transistor, i.e., to maximize the internal power, over the frequency band of interest. In addition, the inductors and capacitors of the LC‐tank were implemented by low‐Q micro‐stripline inductors and high‐Q varactors, respectively, to further improve the locking range of the ILFD. The result shows that a wide locking‐range of 10.2 GHz (from 54.6 GHz to 64.8 GHz (17%)), covering the 57–64‐GHz ultra‐wideband (UWB) set aside by FCC of USA, was achieved. The ILFD can be operated at an input power of −60 dBm. To the authors' knowledge, this is the best input sensitivity ever reported for a 60‐GHz‐band CMOS divider. The power consumption of the ILFD was only 3.39 mW from a 1 V power supply. The chip area was only 0.9 × 0.73 mm2 excluding the test pads. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 518–523, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24970

Tail-injected divide-by-4 quadrature injection locked frequency divider

This article presents a divide-by-4 quadrature injection locked frequency divider (ILFD) employing tunable active inductors (TAIs), which are used to extend the locking range and to reduce die area. The CMOS ILFD is based on a quadrature voltage-controlled oscillator (QVCO) with NMOS cross-coupled switching pairs, two tail MOSFETs and TAI-C tanks, and was fabricated in the 0.35 μm 2P4M CMOS technology. The divide-by-4 LC-tank ILFD is performed by injecting an external signal to the common gate of tail MOSFETs of two coupled VCOs. Measurement results show that at the supply voltage of 2.3 V, the divider free-running frequency is tunable from 0.36 to 1.51 GHz, and at the incident power of 0 dBm the locking range is about 4.6 GHz, from the incident frequency 1.44–6.04 GHz. The core power consumption is 29.37 mW. The die area is 0.976 × 0.812 mm2.

Low power wide‐locking range CMOS quadrature injection‐locked frequency divider

AbstractThis letter presents a new low power and wide‐locking range divide‐by‐2 injection‐locked frequency divider (ILFD). The ILFD consists of a new 5.35 GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18 μm CMOS technology and the core power consumption is 5.72 mW at the supply voltage of 0.8 V. The free‐running frequency of the QILFD is tunable from 5.24 to 5.55 GHz. At the input power of 0 dBm, the divide‐by‐2 locking range is from 8.2 to 13.3 GHz as the tuning voltage is biased at 0.8 V. The phase noise of the locked output spectrum is lower than that of free running ILFD in the divide‐by‐2 mode. The phase deviation of quadrature output is about 1.28°. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2420–2423, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24640

A wide-locking range 6-phase divide-by-3 injection-locked frequency divider

A 6-phase divide-by-3 CMOS injection locked frequency dividers (ILFDs) have been proposed and implemented in a 0.35 μm CMOS process. The ILFD circuits are realised with a 3-stage double cross-coupled CMOS ring oscillator. The self-oscillating voltage controlled oscillator (VCO) is injection-locked by 3th-harmonic input to obtain the division factor of 3. Measurement results show that as the supply voltage varies from 1.2 to 3.5 V, the free-running frequency is from 0.136 to 0.7 GHz. At the incident power of −5 dBm, the locking range in the divide-by-3 mode is from the incident frequency 0.38–2.31 GHz.

A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider

A high-frequency CMOS injection-locked frequency divider (ILFD) is presented by using the distributed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> , series inductor peaking, and multiple-injection techniques. The theoretical analysis for the aforementioned techniques will be given. This ILFD has been fabricated in a 65-nm CMOS process. The core area is 0.4 mm times 0.36 mm without pads. The measured locking range is from 104 to 112.8 GHz, and its power consumption is 7.2 mW from a supply of 1.2 V.

A CMOS Direct Injection-Locked Frequency Divider With High Division Ratios

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a 0.18 mum CMOS process and has a chip core size of 68 mum times 70 mum. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.