CMOS Image Sensor Process Research Articles

Analysis of Disparity Information for Depth Extraction Using CMOS Image Sensor with Offset Pixel Aperture Technique.

A complementary metal oxide semiconductor (CMOS) image sensor (CIS), using offset pixel aperture (OPA) technique, was designed and fabricated using the 0.11-µm CIS process. In conventional cameras, an aperture is located on the camera lens. However, in a CIS camera using OPA technique, apertures are integrated as left-offset pixel apertures (LOPAs) and right-offset pixel apertures (ROPAs). A color pattern is built, comprising LOPA, blue, red, green, and ROPA pixels. The disparity information can be acquired from the LOPA and ROPA channels. Both disparity information and two-dimensional (2D) color information can be simultaneously acquired from the LOPA, blue, red, green, and ROPA channels. A geometric model of the OPA technique is constructed to estimate the disparity of the image, and the measurement results are compared with the estimated results. Depth extraction is thus achieved by a single CIS using the OPA technique, which can be easily adapted to commercial CIS cameras.

In-Pixel Aperture CMOS Image Sensor for 2-D and 3-D Imaging

This paper presents a CMOS image sensor with the in-pixel aperture technique for single-chip 2-D and 3-D imaging. In conventional image sensors, the aperture is located at the camera lens. However, in the proposed image sensor, the aperture is integrated on the CMOS image sensor chip and is formed at a metal layer of the CMOS image sensor (CIS) process. A pixel array of the image sensor is composed of the W, R, B, and PA pixels (W pixel with integrated metal aperture) for extracting color and depth information. While the image of the W pixel becomes blurred with increasing distance from a focused object, the image of the PA pixel maintains the sharpness. Therefore, the depth image can be obtained using the depth from the defocus method. The size of the pixel, which is based on a four-transistor active pixel sensor with pinned photodiode, is $2.8 \,\,\mu {\mathrm{ m}} \times 2.8\,\,\mu \text{m}$ . A prototype of the proposed image sensor was fabricated using the 0.11- $\mu \text{m}$ CIS process and its performance was evaluated.

CMOS depth sensor with programmable filter circuits for environment‐adaptive noise suppression

This Letter introduces a CMOS depth sensor with a multi-resolution single-photon avalanche diode (SPAD) array and area-efficient filter circuit with a programmable reference for environment-adaptive noise suppression. Four SPADs compose a macro-pixel for detecting targets at a short distance with high resolution, whereas 4 × 4 SPADs are reconfigured to a super-pixel for a long distance with enhanced signal-to-noise ratio. To provide environment-adaptive noise suppression in the miniaturised SPAD array, an area-efficient filter circuit with a programmable reference is proposed: a digital macro-filter corresponding to a macro-pixel and an analogue super filter corresponding to a super-pixel. The prototype chip was fabricated with a 110 nm CMOS image-sensor process, including 128 SPAD farm arrays and 128 analogue front-end circuits. With high background light of over 90 klx and a high dark-count rate of over 27.1 kHz, the time-of-flight could be measured by filtering out invalid pulses from noise without using multiple time-to-digital converters per pixel, which enables the implementation of miniaturised LiDAR-sensor systems on a chip.

A Compressive Sensing-Based CMOS Image Sensor With Second-Order $\Sigma \Delta$ ADCs

This paper presents a new analog-to-digital conversion scheme for a second-order $\Sigma \Delta $ incremental analog to digital converter (ADC) that can be employed in a compressive sensing (CS)-based CMOS image sensor (CIS) as a column-parallel ADC. The conversion scheme removes image distortion from a reconstructed image by making the ADC output codes represent an average of the ADC inputs. In addition, a new multiplexing scheme implementing a compressive sensing matrix helps to reduce hardware complexity and control compression ratio without hardware modifications. A $160\times 160$ pixel CS-based CIS fabricated in $0.11~\mu \text{m}$ CIS process successfully demonstrates the proposed schemes.

A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

This paper presents a CMOS image sensor (CIS) utilizing a noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While the noise-shaping SAR ADC with a proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, the delta-readout scheme reduces its power consumption. A prototype $1920\times 1440$ pixel CIS was fabricated in a 90-nm CIS process. A single-channel readout SAR ADC occupying an area of ${22.4}\,\,\mu \textsf {m}\times {715}\,\,\mu \text{m}$ was implemented for reading out 16 columns of pixel array, consuming $437~\mu \text{W}$ . Owing to the proposed noise-shaping SAR ADC with oversampling ratio of 16, this paper achieves a noise reduction of 14 dB compared with the noise of a conventional SAR ADC. The delta-readout reduces the power consumption of the SAR ADC by 10% due to the high hit rate of the full high definition image format. The measured differential nonlinearity of the ADC is +0.77/ −0.54 LSB and the integral nonlinearity is +0.81/ −0.5 LSB. The prototype CIS consumes a total power of 64 mW and achieves a dynamic range of 66.5 dB and a figure of merit of $127~\mu \text{V}\cdot $ nJ at a data rate of 138 Mpixels/s.

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications.

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

An asynchronous data-driven readout prototype for CEPC vertex detector

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 [Formula: see text]m. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

A 0.5erms−Temporal Noise CMOS Image Sensor With Gm-Cell-Based Pixel and Period-Controlled Variable Conversion Gain

A deep subelectron temporal noise CMOS image sensor (CIS) with a Gm-cell based pixel and a correlated-double charge-domain sampling technique has been developed for photon-starved imaging applications. With the proposed technique, the CIS, which is implemented in a standard 0.18- $\mu \text{m}$ CIS process, features pixel-level amplification and achieves an input-referred noise of 0.5 erms− with a correlated double sampling period of $5~ \mu \text{s}$ and a row read-out time of $10~\mu \text{s}$ . The proposed structure also realizes a variable conversion gain (CG) with a period-controlled method. This enables the read-out path CG and the noise-equivalent number of electrons to be programmable according to the application without any change in hardware. The experiments show that the measured CG can be tuned from $50~\mu \text{V}$ /e- to 1.6 mV/e- with a charging period from 100 ns to $4~\mu \text{s}$ . The measured characteristics of the prototype CIS are in a good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

Photon-number-resolving megapixel image sensor at room temperature without avalanche gain

In several emerging fields of study such as encryption in optical communications, determination of the number of photons in an optical pulse is of great importance. Typically, such photon-number-resolving sensors require operation at very low temperature (e.g., 4 K for superconducting-based detectors) and are limited to low pixel count (e.g., hundreds). In this paper, a CMOS-based photon-counting image sensor is presented with photon-number-resolving capability that operates at room temperature with resolution of 1 megapixel. Termed a quanta image sensor, the device is implemented in a commercial stacked (3D) backside-illuminated CMOS image sensor process. Without the use of avalanche multiplication, the 1.1 μm pixel-pitch device achieves 0.21e− rms average read noise with average dark count rate per pixel less than 0.2e−/s, and 1040 fps readout rate. This novel platform technology fits the needs of high-speed, high-resolution, and accurate photon-counting imaging for scientific, space, security, and low-light imaging as well as a broader range of other applications.

High Conversion-Gain Pinned-Photodiode Pump-Gate Pixels in 180-nm CMOS Process

This paper presents the design and characterization of high conversion-gain pixels in a 180-nm CMOS image sensor process. By reducing overlapping capacitance between a floating diffusion and transfer gate, output-referred pixel conversion gain as high as 118uV/e- and read noise as low as 1.8e- rms are experimentally achieved without significant lag. A dark current of 38 pA/cm2 is measured at 60 °C. Comparison between the proposed devices and a baseline pixel regarding device structure and characterization results is also presented.

A 7 ke-SD-FWC 1.2 e-RMS Temporal Random Noise 128×256 Time-Resolved CMOS Image Sensor With Two In-Pixel SDs for Biomedical Applications.

A large full well capacity (FWC) for wide signal detection range and low temporal random noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two in-pixel storage diodes (SDs) has been developed and presented in this paper. For fast charge transfer from photodiode to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large SD-FWC of approximately 7ke-, low temporal random noise of 1.2e-rms at 20fps with true correlated double sampling operation and fast intrinsic response less than 500 ps at 635nm. The proposed imager has an effective pixel array of and a pixel size of . The sensor chip is fabricated by Dongbu HiTek 1P4M 0.11 CIS process.

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

This paper presents a CMOS image sensor (CIS) that extracts a multi-level edge image as well as a human-friendly normal image in a real time from conventional pixels for machine-vision applications, utilizing a proposed speed/power-efficient dual-mode successive-approximation register analog-to-digital converter (SAR ADC). The proposed readout scheme operates in two modes, fine step SAR (FS-SAR) mode and coarse-step single-slope (CS-SS) mode, depending on the difference ( $\Delta $ ) between a chosen pixel and the previous pixel. If a chosen pixel is at a boundary of an object with a large $\Delta $ from the previous pixel, the readout ADC works in the CS-SS mode to readout the edge strength (ES), while the FS-SAR mode is applied for other pixels. By displaying the ES, a multi-level edge image can be obtained in a real time along with a normal image with no hardware/time overhead. By saving the MSBs conversion cycles regardless of $\Delta $ , the proposed dual-mode readout scheme enhances the readout speed and reduces power consumption. A prototype QQVGA CIS with 10-bit SAR ADCs was fabricated in a 0.18- $\mu \text{m}$ 1P4M CMOS image sensor process with a 4.9- $\mu \text{m}$ pixel pitch. With a maximum pixel rate of 61.4 Mp/s, the prototype demonstrated figure of merits of 70 pJ/pixel/frame, 0.35 $\text{e}^{-}\cdot \text {nJ}$ , and 0.34 $\text{e}^{-}\cdot \text {pJ}$ /step.

A process modification for CMOS monolithic active pixel sensors for enhanced depletion, timing performance and radiation tolerance

For the upgrade of its Inner Tracking System, the ALICE experiment plans to install a new tracker fully constructed with monolithic active pixel sensors implemented in a standard 180 nm CMOS imaging sensor process, with a deep pwell allowing full CMOS within the pixel. Reverse substrate bias increases the tolerance to non-ionizing energy loss (NIEL) well beyond 10131MeVneq∕cm2, but does not allow full depletion of the sensitive layer and hence full charge collection by drift, mandatory for more extreme radiation tolerance. This paper describes a process modification to fully deplete the epitaxial layer even with a small charge collection electrode. It uses a low dose blanket deep high energy n-type implant in the pixel array and does not require significant circuit or layout changes so that the same design can be fabricated both in the standard and modified process. When exposed to a 55Fe source at a reverse substrate bias of −6 V, pixels implemented in the standard and the modified process in a low and high dose variant for the deep n-type implant respectively yield a signal of about 115 mV, 110 mV and 90 mV at the output of a follower circuit. Signal rise times heavily affected by the speed of this circuit are 27.8+∕−5 ns, 23.2+∕−4.2 ns, and 22.2+∕−3.7 ns rms, respectively. In a different setup, the single pixel signal from a 90Sr source only degrades by less than 20% for the modified process after a 10151MeVneq∕cm2 irradiation, while the signal rise time only degrades by about 16+∕−2 ns to 19+∕−2.8 ns rms. From sensors implemented in the standard process no useful signal could be extracted after the same exposure. These first results indicate the process modification maintains low sensor capacitance, improves timing performance and increases NIEL tolerance by at least an order of magnitude.

Octagonal CMOS Image Sensor for Endoscopic Applications

An octagonal shaped CMOS image sensor (CIS) has been developed for endoscopic applications. The octagonal shape of the outlined die is also applied to the pixel matrix which has suppressed corners, resulting in an octagonal pixel matrix of 422'640 effective pixels. The sensor die fits on a circumference of 3.2 mm diameter being this the best die cut ratio between the cut corners and the pixel placement. The missing pixels on the corners are internally compensated by the readout electronics to maintain a rectangular image output format of 680x680 pixels. This paper presents the solutions found to overcome the layout challenges of fitting both row and column logic on the same side of the diagonally cut corners. Furthermore, the sensor features an area efficient column parallel ADC converter, having on the column readout side, only 402 μm overhead total space between the utmost pixel row until the edge of the silicon die. This space is used to place CDS, ADC, column addressing, readout, additional electronics and power routing. The sensor also has a fully autonomous operation, requiring only an external clock supply to drive the internal state machine. The interface requires just 6 connections: 2 for power supply, 2 for bidirectional data and 2 for main clock supply. The frame rate and the exposure are configurable by register. The maximum frame rate is 50 frames per second (FPS) and data is delivered over LVDS serial data link. The integration time can be configured from 147 μs to 20.1 ms. The power supply is 3.3 V with internal Power-On-Reset (POR) and has a power consumption of 91 mW manufactured in 180 nm CIS process.

Analytical Modeling and TCAD Simulation of a Quanta Image Sensor Jot Device With a JFET Source-Follower for Deep Sub-Electron Read Noise

A novel quanta image sensor (QIS) jot device with a CMOS compatible junction-field effect transistor (JFET) source follower (SF) is introduced. The device is proposed to further reduce the read noise of QIS jots and ultimately realize a read noise of 0.15e-r.m.s. for accurate photoelectron counting. We take advantage of the small gate capacitance in a p-channel JFET SF to reduce the total capacitance of the floating diffusion, which yields a greatly improved conversion gain of 1.38 mV/e- in TCAD simulation compared to MOSFET SF with the same pitch size. Lower 1/ ${f}$ noise is also anticipated yielding a low input-referred read noise. The device is designed in a 45 nm CMOS image sensor process. The fundamental working principles of this device are discussed, and important functionalities are analyzed with simulation and theory.

Fully Depleted Pinned Photodiode CMOS Image Sensor With Reverse Substrate Bias

A new pixel design using fully depleted pinned photodiode (PPD) in a 180-nm CMOS image sensor (CIS) process has been developed and the first experimental results from a test chip are presented. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the in-pixel p-wells have been added to the manufacturing process in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The new design shows the same electro-optical performance as the PPD pixel it is based on, and can be fully depleted without significant leakage currents. This development has the potential to greatly increase the quantum efficiency of scientific PPD CIS at near-infrared and soft X-ray wavelengths.

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

A Tileable CMOS X-Ray Line Detector Using Time-Delay-Integration With Pseudomultisampling for Large-Sized Dental X-Ray Imaging Systems

This paper presents a low-power and low-noise tileable CMOS X-ray line detector with time-delay-integration (TDI) for large-sized dental X-ray imaging systems. The proposed X-ray line detector with TDI adopts pseudomultisampling (PMS) using shifted clocks for the single-slope analog-to-digital converter (ADC) to reduce the required clock cycles for the ADC. The reduced clock cycle decreases the dynamic power and power fluctuation to ensure power stability for large-sized X-ray detectors. The TDI X-ray line detector with PMS was fabricated using 0.18- $\mu \text{m}$ CMOS image sensor process technology with a stitching process, which has an image format of 1010 $\times $ 86 and a pixel size of $75\,\,\mu \text{m}\,\,\times 75\,\,\mu \text{m}$ . The X-ray line detectors are tiled with $1 \times 2$ and $1\,\,\times3$ arrays to enlarge the active areas for dental panoramic and cephalometric X-ray imaging systems, respectively. The measurement results show the random noise of 0.43 LSB and a dynamic range of 78.5 dB, when the number of TDI stages is 86 and the number of PMS steps is 4. The dynamic current and power consumption per ADC are reduced from 157.4 $\mu \text{A}$ and $283.32~\mu \text{W}$ to $41.2~\mu \text{A}$ and 74.16 $\mu \text{W}$ , respectively, when PMS is adopted for TDI.

Development of a 55 μm pitch 8 inch CMOS image sensor for the high resolution NDT application

A CMOS image sensor (CIS) with a large area for the high resolution X-ray imaging was designed. The sensor has an active area of 125 × 125 mm2 comprised with 2304 × 2304 pixels and a pixel size of 55 × 55 μm2. First batch samples were fabricated by using an 8 inch silicon CMOS image sensor process with a stitching method. In order to evaluate the performance of the first batch samples, the electro-optical test and the X-ray test after coupling with an image intensifier screen were performed. The primary results showed that the performance of the manufactured sensors was limited by a large stray capacitance from the long path length between the analog multiplexer on the chip and the bank ADC on the data acquisition board. The measured speed and dynamic range were limited up to 12 frame per sec and 55 dB respectively, but other parameters such as the MTF, NNPS and DQE showed a good result as designed. Based on this study, the new X-ray CIS with ∼ 50 μm pitch and ∼ 150 cm2 active area are going to be designed for the high resolution X-ray NDT equipment for semiconductor and PCB inspections etc.

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta-readout ( $\Delta $ -readout) scheme reads the signal difference between two pixels located next to each other ( $\Delta _{\mathrm {pixel}}$ ) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by the $\Delta $ -window checking, the proposed $\Delta $ -readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a $0.18~\mu \text {m}~1$ P4M CIS process with a $4.4~\mu \text {m}$ pixel pitch, where each single ADC occupies an area of $70\,\,\mu \text {m}\,\,\times \,\,500\,\,\mu \text {m}$ . The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.