Characteristics Of CMOS Devices Research Articles

A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation

High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc.

Cryogenic DC Characteristics of Low Threshold Voltage (VTH) n-channel MOSFETs

Cryogenic electronics has grown in its widespread use for various technological applications. Particularly, CMOS devices and circuits are more frequently used in such systems due to their dominance in the electronics industry. At cryogenic temperatures, characteristics of CMOS devices vary, which should be characterized with measurements. In this paper, the changes in the electronic behavior of a low threshold voltage (VTH) n-channel MOSFET (nMOSFET) are captured experimentally. The results are then compared with the measurements of a regular nMOSFET having the same channel width and length. It is shown that although the VTH increase of both transistors is at the same amount, this value corresponds to a more significant percentage of the nominal threshold voltage for the low VTH nMOSFET.

Key technologies for dual high-k and dual metal gate integration**Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al–O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1 (NH4OH:H2O2:H2O = 1 :1 : 5) and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON. After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Deactivation Improvement of Advanced CMOS Devices Using a Flood BC PLAD Process

Flood buried-contact (FBC) plasma doping (PLAD) is a promising scheme to improve both pMOS and nMOS device performance with a significant cost reduction. Deactivation characteristics of CMOS devices doped by an FBC implant using an ultra-low energy (ULE) BF3 PLAD process is extensively evaluated from inline [front end of line (FEOL)] to final [back end of line (BEOL)] to investigate the impact of the backend thermal processing. nMOS devices show more serious deactivation than pMOS devices from FEOL to BEOL. However, both pMOS and nMOS devices obtained further improvements at BEOL processing. The mechanism of nMOS device performance improvement can be attributed to the Schottky barrier height lowering effect and carrier deactivation improvement, as well as other effects including silicide stability improvement and mechanical stress. It is observed that the deactivation of nMOS device can be improved by an ULE BF3 PLAD process which can be interpreted by less dopant loss and $F$ passivation on the interface between the source/drain and the dielectric spacer. Another important observation is that the deactivation improvement is more profound for the small-size devices. Deactivation characteristics of CMOS devices are consistent with our recent deactivation mechanism studies of blanket wafers (electrical-assisted diffusion mechanism), and provide further evidence for this mechanism.

Design of an Advanced CMOS Power Amplifier

The CMOS power amplifier (PA) is a promising solution for highly-integrated transmitters in a single chip. However, the implementation of PAs using the CMOS process is a major challenge because of the inferior characteristics of CMOS devices. This paper focuses on improvements to the efficiency and linearity of CMOS PAs for modern wireless communication systems incorporating high peak-to-average ratio signals. Additionally, an envelope tracking supply modulator is applied to the CMOS PA for further performance improvement. The first approach is enhancing the efficiency by waveform engineering. In the second approach, linearization using adaptive bias circuit and harmonic control for wideband signals is performed. In the third approach, a CMOS PA with dynamic auxiliary circuits is employed in an optimized envelope tracking (ET) operation. Using the proposed techniques, a fully integrated CMOS ET PA achieves competitive performance, suitable for employment in a real system.

Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2–5× higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65nm CMOS devices. Specifically, p+/n ultra-shallow junctions formed with BF3 plasma doping have superior Xj/Rs characteristics to beamline implants and yield up to 30% lower Rs for 20nm Xj while using standard spike anneal with ramp-up rate of 75°C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior Vt roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65nm devices with PLAD SDE implants while still achieving Vt roll-off and Ion−Ioff performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity.

An investigation on RF CMOS stability related to bias and scaling

In recent times, CMOS devices have played an increasing important role in the area of RF-ICs to implement part of the high-frequency circuits. As a result, the high-frequency characteristics of CMOS devices, including stability, should be investigated in-depth. In the design of RF amplifier, the consideration to avoid oscillation in the circuits is a must. Basically, the instability involved in designing RF circuits can be reduced if the transistor is stable in the interesting frequency region. In this study, the stability factor of CMOS device is discussed. First, the stability factor (i.e. k-factor) is derived based on the microwave small-signal model of MOSFET. Therefore, small-signal parameters that affect stability can be carefully examined. In addition, the effects of biasing and dimensions on k-factor are also discussed. Since various operating point (or biasing) can cause device to have different effects on high frequency, the correlation between biasing and stability is discussed in this study. Due to the fact that CMOS device has continuously shrunk in size, a detailed discussion of the effect of MOSFETs dimension on stability is included. It is found from our experimental results that the smaller the gate length, the greater is the frequency range for CMOS device to become potentially unstable.

Metallized ultra-shallow-junction device technology for sub-0.1 μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 /spl mu/m MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability. >

Co-integration of optoelectronics and submicrometer CMOS

The rapid emergence of multichip modules (MCMs) and the continuing interest in wafer scale integration (WSI) provide important opportunities for successful insertion of high performance optical interconnections into real systems. The large area substrates and the distances between packaged wafer-level modules introduce distances of sufficient length that propagation of very high-speed digital signals along electrical lines will be difficult. At the same time, the substrates allow use of thin film technologies for fabrication of optoelectronic devices, optical waveguides, and other optical elements, drawing on the natural alignment accuracy of photolithographic definition of optical components to avoid several practical problems arising when optical elements are surface mounted. For such reasons, large area silicon wafers provide an important potential application for more aggressive use of optical interconnections. An important issue is growth of GaAs semiconductor regions within a silicon WSI or MCM substrate containing high performance silicon CMOS circuitry, seeking to co-integrate optical and silicon VLSI devices. Experimental studies of submicrometer CMOS device characteristics following thermal simulation of GaAs heteroepitaxial growth are summarized. >

Sub-Micron Contact Filling and Electromigration of Selfion-Enhanced Physical Vapor Deposited Aluminum Films

ABSTRACTThe electromigration resistance, the sub-micron contact area filling capability, the crystal structure, the preferred orientation, and the CMOS device characteristics of self-ion-enhanced physical vapor deposited aluminum metallizations have been studied. It has been found that optimal conditions can be achieved by increasing the deposition rate and by applying some ionization and acceleration of the aluminum particles.

Digital characteristics of CMOS devices at cryogenic temperatures

The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V/sub II/ and V/sub IH/ increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V/sub H/-V/sub I/, and V/sub IH/-V/sub II/ all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the beta /sub N// beta /sub P/ ratio as the temperature is lowered. >

Characteristics of CMOS devices in high-energy boron-implanted substrates

CMOS devices on substrates subject to high-energy implantation of boron for buried-layer fabrication are examined. FET device characteristics, threshold voltage, and breakdown characteristics are investigated, along with mobility and minority-carrier lifetime. In addition, well leakage and breakdown are studied in an effort to provide guidelines for well design in an megaelectronvolt-implanted substrate. It is seen that MOSFET transistor characteristics are virtually unaffected by the implant. Latchup behavior improves with the incorporation of the buried layer, and the holding voltage increases as the well and implant depths decrease.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The characteristics of CMOS devices in oxygen-implanted silicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25*10/sup 18/ cm/sup -2/ to 1.4*10/sup 18/ cm/sup -2/ . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4*10/sup 17/ cm/sup -2/ oxygen dose and annealed at 1150 degrees C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal. >

Fabrication of SOI CMOS over large-area continuous-oxide films formed using epitaxial lateral overgrowth techniques

The authors have developed techniques for producing thin, monocrystalline silicon films over large area continuous oxides using the epitaxial lateral overgrowth (ELO) approach and have investigated the electrical characteristics of CMOS devices fabricated in these films. A conventional ELO process using a growth-etchback technique to eliminate spurious nucleation was used to overgrow single-crystal silicon from seed regions over the oxide stripes. Silicon nitride was deposited and patterned with a mask which had an identical pattern to the first mask. After nitride etch, the original seed region was exposed. A partial silicon etch was performed and the wafers were then reoxidized. During this step an oxide was grown over the exposed seed region which subsequently coalesced with the initial oxide stripes, forming a continuous insulating region covered by stripes of single-crystal silicon. These formed the seed for a second ELO step that resulted in a continuous single-crystal silicon film over the underlying oxide. The transistors, fabricated in ELO material, exhibited electrical characteristics comparable to both SOS controls and to devices fabricated on SIMOX (silicon implanted with oxygen) wafers in the laboratory using an identical process. >

Total Dose Characterizations of CMOS Devices in Oxygen Implanted Silicon-on-Insulator

The total dose characteristics of CMOS devices fabricated in oxygen implanted buried oxide silicon-on-insulator (SOI) substrates with different post-implant annealing processes are studied. The threshold voltage shift, subthreshold slope degradation and mobility degradation of front channel SOI/CMOS devices are measured to be the same as those of bulk devices processed identically. Negative substrate bias lowers the threshold voltage shift of back channel SOI transistors, while not affecting the front channel characteristics. Under present processing conditions, the radiation characteristics of front channel devices are independent of the postoxygen-implant annealing temperature. Oxygen precipitates at the silicon/buried oxide interface enhance interface state generation of the back channel devices during irradiation.