Deactivation Improvement of Advanced CMOS Devices Using a Flood BC PLAD Process

Abstract

Flood buried-contact (FBC) plasma doping (PLAD) is a promising scheme to improve both pMOS and nMOS device performance with a significant cost reduction. Deactivation characteristics of CMOS devices doped by an FBC implant using an ultra-low energy (ULE) BF3 PLAD process is extensively evaluated from inline [front end of line (FEOL)] to final [back end of line (BEOL)] to investigate the impact of the backend thermal processing. nMOS devices show more serious deactivation than pMOS devices from FEOL to BEOL. However, both pMOS and nMOS devices obtained further improvements at BEOL processing. The mechanism of nMOS device performance improvement can be attributed to the Schottky barrier height lowering effect and carrier deactivation improvement, as well as other effects including silicide stability improvement and mechanical stress. It is observed that the deactivation of nMOS device can be improved by an ULE BF3 PLAD process which can be interpreted by less dopant loss and $F$ passivation on the interface between the source/drain and the dielectric spacer. Another important observation is that the deactivation improvement is more profound for the small-size devices. Deactivation characteristics of CMOS devices are consistent with our recent deactivation mechanism studies of blanket wafers (electrical-assisted diffusion mechanism), and provide further evidence for this mechanism.