Current-mode CMOS Research Articles

A 2.4 GHz Wide-Range CMOS Current-Mode Class-D PA with HD2 Suppression for Internet of Things Applications.

Short-range Internet of Things (IoT) sensor nodes operating at 2.4 GHz must provide ubiquitous wireless sensor networks (WSNs) with energy-efficient, wide-range output power (POUT). They must also be fully integrated on a single chip for wireless body area networks (WBANs) and wireless personal area networks (WPANs) using low-power Bluetooth (BLE) and Zigbee standards. The proposed fully integrated transmitter (TX) utilizes a digitally controllable current-mode class-D (CMCD) power amplifier (PA) with a second harmonic distortion (HD2) suppression to reduce VCO pulling in an integrated system while meeting harmonic limit regulations. The CMCD PA is divided into 7-bit slices that can be reconfigured between differential and single-ended topologies. Duty cycle distortion compensation is performed for HD2 suppression, and an HD2 rejection filter and a modified C-L-C low-pass filter (LPF) reduce HD2 further. Implemented in a 28 nm CMOS process, the TX achieves a wide POUT range of from 12.1 to -31 dBm and provides a maximum efficiency of 39.8% while consuming 41.1 mW at 12.1 dBm POUT. The calibrated HD2 level is -82.2 dBc at 9.93 dBm POUT, resulting in a transmitter figure of merit (TX_FoM) of -97.52 dB. Higher-order harmonic levels remain below -41.2 dBm even at 12.1 dBm POUT, meeting regulatory requirements.

Design of current steering logic CMOS circuit

The current-mode CMOS technology has many positive identities, while traditional current-mode CMOS circuits designing methods is comparatively more complex than voltage-mode CMOS. In this paper, using threshold logic, a current-mode CMOS circuits designing method based on spectral techniques is proposed. The proposed method is capable of designing combinational logic current-mode CMOS circuits. The sequential logic current-mode CMOS circuits can also be designed with the designed combinational logic current-mode CMOS circuit. The designed circuit is steered only by current signals. By using both simulations and real circuit tests, we proved the effectiveness of the proposed circuit designing method. Using HSPICE simulations, the designed circuit is proven to have advantages including lower circuit power consumption and higher stability of the current through power supply compared with voltage-mode CMOS and other main current-mode CMOS circuits, and the designed circuits require less control signals than other major current-mode CMOS circuits.

A low-voltage MOS translinear loop, biased using FVF and its applications in realizing square-rooter and squarer circuits

In this paper, a new MOS Translinear Loop (MTL), biased using Flipped-Voltage-Follower, has been presented and its use in the CMOS Current-Mode (CM) realization of the non-linear functional circuits namely, square-rooting and squaring has been demonstrated. The new MTL facilitates the low-voltage operation of the proposed CMOS CM circuits while maintaining all the MOSFETs operating in strong inversion mode. The workability of both the proposed circuits has been validated by simulations carried out on Cadence Virtuoso software using 0.18 μm CMOS technology at a DC power supply voltage of 0.85 V and the results of the same have been presented. Furthermore, temperature and corner analyses have been performed to verify the robustness of the proposed circuits in the practical environment.

A Novel Pseudo-Taylor-Exponential Approximation Technique for Input–Output Range Extension with Reduced Linearity Error and its Current-Mode CMOS Implementation

A novel mathematical approach has been proposed for input–output range extension of Pseudo-Taylor-Exponential-Approximation (PTEA) for achieving over seven-decade exponential function, while reducing the linearity error by 1 dB and attaining simple coefficients such as to realize this technique in designing the MOSFET based circuit. This new MPTEA technique, has been successfully utilized for its current-mode (I-I) CMOS implementation involving translinear principle of MOSFETs in weak inversion (WI) region. The CMOS synthesis procedure has been detailed and relevant second-order effects consists of noise, bulk-effect etc. have been explored. For post-layout simulations of the synthesized CMOS implementation, the SPECTRE simulation tool from Cadence, with 180 nM CMOS parameters, has been utilized to justify its practical workability. The proposition, in its CMOS layout, occupies an area of 0.0126mm2 only. It consumes only ≈4.92 μW static power by utilizing ± 0.65 V power supply and produces 146.5 dB range of linear-in-dB output with ± 1 dB linearity error.

Current-Mode Self-Amplified CMOS Sensor Intended for 2D Temperature Microgradients Measurement and Imaging.

This paper presents the design of a current-mode CMOS self-amplified imager operating in dark conditions, for thermal imaging, which provides an innovative solution for precision thermal contact mapping. Possible applications of this imager range from 3D CMOS integrated circuits to the study of in-vivo biological samples. It can provide a thermal map, static or dynamic, for the measurement of temperature microgradients. Some adaptations are required for the optimization of this self-amplified image sensor since it responds exclusively to the dark currents of the photodiodes throughout the array. The sensor is designed in a standard CMOS process and requires no post-processing steps. The optimized image sensor operates with integration times as low as one and can achieve both SNR and dynamic range compatible to those of sensors available on the market, estimated as and , respectively; noise equivalent temperature difference can be as low as ; and detection errors as low as ±. Furthermore, under optimal conditions the self-amplification process enables a simple form of CDS, enhancing the overall sensor noise performance.

High-PSRR, Low-Voltage CMOS Current Mode Reference Circuit Using Self-Regulator with Adaptive Biasing Technique

High-PSRR, Low-Voltage CMOS Current Mode Reference Circuit Using Self-Regulator with Adaptive Biasing Technique

Digital Evolution of the Quadrature Balanced Power Amplifier Transceiver for Full Duplex Wireless Operation

This letter compares analog and digital implementations of quadrature balanced power amplifier (QBPA) transceiver for full-duplex wireless operation. The design considerations of both architectures are laid out, and a comprehensive performance comparison between the two approaches based on theoretical and experimental results is proposed. For this end, a new QBPA chip prototype employing voltage-mode switched-capacitor RF DACs was fabricated in TSMC’s 65 nm CMOS, whereas the analog QBPA, reported in our previous work, comprises 180 nm CMOS current-mode class-AB PAs. We demonstrate that while both techniques can achieve deep interference cancellation, the switched-capacitor QBPA (SC-QBPA) exhibits considerably better performance in terms of noise figure (NF), linearity, and system efficiency. At 8 dB backoff from 20 dBm peak TX power, the SC-QBPA achieves 17 dB improvement in NF and 10 dB better linearity. The analog QBPA, on the other hand, can reach higher operating frequencies and has 1.4 dB lower RX insertion loss.

5-㎒ Pseudo-differential Current-mode CMOS Relaxation VCO with Temperature Stability of 41.8 ppm/℃

5-㎒ Pseudo-differential Current-mode CMOS Relaxation VCO with Temperature Stability of 41.8 ppm/℃

A current-mode system to self-measure temperature on implantable optoelectronics

BackgroundOne of the major concerns in implantable optoelectronics is the heat generated by emitters such as light emitting diodes (LEDs). Such devices typically produce more heat than light, whereas medical regulations state that the surface temperature change of medical implants must stay below + 2 °C. The LED’s reverse current can be employed as a temperature-sensitive parameter to measure the temperature change at the implant’s surface, and thus, monitor temperature rises. The main challenge in this approach is to bias the LED with a robust voltage since the reverse current is strongly and nonlinearly sensitive to the bias voltage.MethodsTo overcome this challenge, we have developed an area-efficient LED-based temperature sensor using the LED as its own sensor and a CMOS electronic circuit interface to ensure stable bias and current measurement. The circuit utilizes a second-generation current conveyor (CCII) configuration to achieve this and has been implemented in 0.35 μm CMOS technology.ResultsThe developed circuits have been experimentally characterized, and the temperature-sensing functionality has been tested by interfacing different mini-LEDs in saline models of tissue prior to in vivo operation. The experimental results show the functionality of the CMOS electronics and the efficiency of the CCII-based technique with an operational frequency up to 130 kHz in achieving a resolution of 0.2 °C for the surface temperature up to + 45 °C.ConclusionsWe developed a robust CMOS current-mode sensor interface which has a reliable CCII to accurately convey the LED’s reverse current. It is low power and robust against power supply ripple and transistor mismatch which makes it reliable for sensor interface. The achieved results from the circuit characterization and in vivo experiments show the feasibility of the whole sensor interface in monitoring the tissue surface temperature in optogenetics.

Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology

The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.

Design of a range-segmented CMOS current-mode exponential circuit

Design of a range-segmented CMOS current-mode exponential circuit

A 1.2-V Current-Mode RMS-to-DC Converter Based on a Novel Two-Quadrant Electronically Simulated MOS Translinear Loop

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a squarer/divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130-nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system.

On the realisation of current-mode four-quadrant CMOS cuber

For the first time, a fully current-mode CMOS cube-law generator (cuber) that gives output in four quadrants is presented. The proposed circuit design is based on translinear principle of MOSFETs operating in weak inversion region. The details on circuit synthesis have been given and the second-order effects on the performance of the cuber have also been considered in this communication. Validation by post-layout simulation have been carried out on Virtuoso-SPECTRE tool with 180 nm GPDK CMOS process parameters. It has been found that using ± 0.5 V supply voltage, the realized current mode cuber circuit works for an input range of ± 200 nA (± 8 normalized input range) while consuming only 139.9 nW static power and contributes a maximum of ± 1.5 dB error over a wide input range of ± 25 nA to ± 200 nA in all four-quadrants.

CMOS analog filter design using the Proportional Source Transconductances Integrator

This work assesses the applicability of a compact CMOS current-mode companding integrator in the design of analog continuous-time filters with high linearity. The companding integrator is based on the proportionality between the source transconductances of the input and output MOS transistors and is independent of the inversion level of the devices. The circuit has been designed in CMOS 130 nm technology with approximately 90 μm2 total active area including biasing elements. According to simulation results the integrator performs a useful frequency bandwidth of up to 4 MHz and a third order intermodulation distortion smaller than −47 dB for input amplitudes ranging from 100 nA to 1 μA. The small and large signal responses and the third order intermodulation, among other features, have also been analyzed through simulation for a fourth order low-pass filter and a sixth order bandpass filter. Performance is compared with a CMOS log-domain integrator and filter.

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a gm/ID based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90nm and UMC 130nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.

0.3 V 2.5 nW per Channel Current-Mode CMOS Perceptron for Biomedical Signal Processing in Amperometry

This paper describes an implementation of a preprocessor with a perceptron for applications in amperometry. The perceptron operates in the current mode, in the weak-inversion area and makes it possible to process analog current signals with values below 1 nA. This paper presents an axon structure consisting of six transistors and a programmable dendrite with a fully digital interface implementing weights with an accuracy of 0.13%. The perceptron implemented in the 65-nm CMOS technology is characterized by a power consumption of 2.5 nW per channel. The data processing frequency of the perceptron equals 1k samples/s. The structure of the preprocessor makes it possible to implement it using a standard digital CMOS technology. The operation of the preprocessor was discussed using an example of a current signal monitor recognizing specified events. This paper discusses the perceptron sensitivity to the dispersion of the supply voltage and operating temperature.

A CMOS current mode four quadrant analog multiplier free from mobility reduction

This paper describes a simple technique for reducing the mobility degradation effect. A current mode squarer circuit and a four quadrant analog multiplier are designed using this technique. The proposed circuits are designed and simulated using the ELDO simulator in 0.18µm CMOS technology with a power supply of ±0.75V. The simulation results of analog multiplier for an input range of ±10 µA that demonstrates a −3dB bandwidth of 300MHz, a 0.15mW of maximum power consumption, a low nonlinearity error of 1.1% and a THD of 0.8% in 1MHz. Monte Carlo simulation of the proposed multiplier is analysed to verify the robustness of the circuit versus the technological process.

Integrable CMOS-Based Current-Mode Sinusoidal Frequency and Peak Detector

This research proposes the integrable CMOS current-mode instantaneous frequency and peak detector (FPD) based on the trigonometric relationships and mathematic algorithm without the divider function and low-pass filter. The proposed FPD structure is straightforward, consisting of two differentiators, two multipliers and one square-rooter. The input of FPD is operable in the 20–100 kHz frequency and 20–100 \({\upmu }\)A amplitude under \({\pm }1.5\) V power supplies. In the research, the FPD was simulated using the current-mode CMOS technology and a prototype detector subsequently materialized using the commercially available components. In addition, the FPD was experimentally utilized as the FM and AM demodulators with very satisfactory demodulation outcomes. The simulation and experimental results were agreeable and also consistent with the trigonometric relationships and algorithmic scheme. More importantly, the integrable FPD could achieve the high-accuracy current output and fast response.

Current mode pulse width modulation/pulse position modulation based on phase lock loop

Abstract In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 μm CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 μA to 109 μA, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 μm × 60 μm.

Implementation and Design of Current-mode PWM Control CMOS Buck Power Converter with Protection Circuits

A lower power consumption, smaller output ripple and better regulation current-mode CMOS buck power converter with a novel on-chip soft-start circuit for feedback control is implemented in this paper. The over-current protection and soft-start circuit can produce a slowly rising output voltage without extra clock or any external component to prevent inrush current and output voltage overshoot during the start-up period of the converter. The converter is designed and simulated using the TSMC 0.18μm MM/RF 1P6M SALICIDE 1.8V/3.3V CMOS process. Hspice simulation results show that, the buck converter having 1.129 1.200mm2 chip size with power efficiency about 90%. This chip can operate with input supply voltage from 2.8V to 3.3V , and its output voltage can stable at 1.2V and less than 22mV ripple voltage at maximum loading current 500mA. The simulation shows the circuit has about 1.0ms of soft-start time and can inhibit the inrush current when the power on.