CMOS Combinational Circuits Research Articles

Особенности импульсных помех в КМОП комбинационных логических элементах при сборе заряда с треков одиночных частиц

Особенности импульсных помех в КМОП комбинационных логических элементах при сборе заряда с треков одиночных частиц

Methods of Improving the Accuracy of Simulating Delays and Peak Currents of Combinational CMOS-Circuits at the Logical Design Level

With the reduction of the technological dimensions of transistors, the influence of the variations of circuit and technological parameters on the values of the delay of the elements of combinational CMOS-circuits has grown significantly. Due to the spread of the values of these parameters, the uncertainty of delays appears, which leads to the necessity to define the ranges of possible delay values. The peak current in power lines when switching the inputs of gates is another factor increasingly influencing the design process of CMOS circuits in the transition to nanometer technologies. The value of the peak current is used to estimate the voltage drop in the power lines, which in turn is necessary to calculate the width of the power lines of CMOS circuits and switch off the transistors in the method of reducing the static power. The methods of full circuit simulation do not comprehensively analyze the circuits with a large number of inputs and the methods at the logical level of designing CMOS circuits do not provide the desired accuracy of the evaluation of the values of the delays and the peak current in the circuit. The problem of increasing the accuracy and the reliability of the analysis of the performance and peak currents of CMOS combinational circuits, taking into account the simultaneous switching of the inputs, as well as the analysis of logical correlations of the signals, is considered. The proposed method is based on using the cubic approximation of the correction difference of delays, taking into account the simultaneous switching of inputs. It is shown that the developed techniques of the analysis of the performance and peak currents of CMOS combinational circuits improve the accuracy of the upper estimates of the analyzed parameters by up to 3% compared with accurate simulation and make it possible to reduce the pessimistic upper estimate by factors of 2 to 3 compared with the estimate of the worst case. The developed methods of improving the accuracy of simulating delays and peak currents of combinational CMOS-circuits can be used as an addition to the existing CADS tools for VLSI for noise-immunity analysis, the analysis of the peak currents, characterization of complex functional units, and improving the accuracy of classical static analysis. To improving the accuracy of the interval estimates of the minimum delays and maximum peak current, the simulation methods taking into account the simultaneous switching of the inputs of the logical element are developed. In relation to the circuit simulation, the error of these methods does not exceed 3%. Compared with the results obtained without taking the simultaneous switching into account, reducing the minimum delay by up to 50% and the pessimistic estimate of the peak current of combinational circuits is reduced on average by 50–55%.

Методы повышения точности моделирования задержек и пиковых токов комбина-ционных КМОП-схем на логическом уровне проектирования

Методы повышения точности моделирования задержек и пиковых токов комбина-ционных КМОП-схем на логическом уровне проектирования

Выбор энергоемких тестовых наборов для обеспечения режима повышенного энергопотребления комбинационных КМОП-схем

Выбор энергоемких тестовых наборов для обеспечения режима повышенного энергопотребления комбинационных КМОП-схем

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits

current in CMOS circuits can be controlled at the circuit level and at the device level as well. One of the circuit level control techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be reduced in the sleep state. In this paper, an algorithm has been given to determine the optimum input vector that can be applied to the circuit in the sleep state for getting low leakage power. This algorithm uses the concept of controllability of the nodes in the circuit and the dependency of a gate on the remaining gates in the circuit to determine the optimum input vector. The proposed algorithm has been applied on an ISCAS benchmark circuit C17, the results showed that the algorithm gives a vector having a leakage nearer to the vector obtained using exhaustive search in CADENCE that gives low leakage value with less execution time as well. Keywordscurrent control, Low leakage vector, VLSI digital circuits, Low leakage power, CMOS combinational circuits.

Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits

This work extends to the switch level the verification and testing techniques based upon boolean satisfiability (SAT), so that SAT-based methodologies can be applied to circuits that cannot be well described at the gate level. The main achieved goal was to define a boolean model describing switch-level circuit operations as a SAT problem instance, to be applied to combinational equivalence checking and bridging-fault test generation. Results are provided for a set of combinational CMOS circuits, showing the feasibility of SAT-based verification and testing of switch-level circuits.

Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits

Single-event transient pulse quenching (Quenching effect) is employed to effectively mitigate WSET (SET pulse width). It enhanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, parameter variation is another serious issue that significantly affects circuit’s performance and single-event response. Monte Carlo simulations combined with TCAD (Technology Computer-Aided Design) simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS (N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) simulation than that in PMOS’ (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor), so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness (TOXE) and channel length variation (XL) mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases. single-event transient (SET), parameter variation, Monte Carlo simulation, quenching effect, charge share

Experimental Estimation of the Window of Vulnerability for Logic Circuits

Accurate estimation of single event upset rates for complex combinational logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS combinational logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30-60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify logic error rate calculations.

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors

Power dissipation and propagation delay are contradicting factors in the design of VLSI CMOS circuits. This paper investigates CMOS circuits with Self-Bias Transistors (SBTs) connected between the pull-up/down network and the supply rails. Previous research on circuits with SBTs shows substantial reduction in leakage power of combinational circuits. We extend the analyses by studying both static and dynamic power and also propagation delay for combinational as well as sequential circuits. Transistor-level dual-Vt technique is employed for combinational circuits with SBTs to achieve a good power and delay trade-off by selecting different transistors in the circuit to have different Vt. Extensive HSPICE simulations were performed with 0.18 μm CMOS technology. Results show that on average, a 45% reduction in static power and 17% reduction in dynamic power can be achieved by employing SBTs in combinational CMOS circuits. Similar results for sequential CMOS circuits are also included. Simulation results for propagation delay and power-delay trade-off are also presented.

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

In this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations.

Ramp Voltage Testing for Detecting Interconnect Open Faults

A method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal is proposed. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper, we show fault detectability and effectiveness of the proposed method by simulation-based and theoretical analysis. We also expose that the method can be applicable to every fault location in a circuit and open faults with any value. Finally, we show ATPG results that are suitable to the proposed method.

Using SAT-based techniques in power estimation

Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the successful deployment of SAT technology in a wide range of applications domains, and particularly in electronic design automation (EDA). SAT is increasingly being used as the underlying model for a number of applications in EDA. This paper describes how to formulate two problems in power estimation of CMOS combinational circuits as SAT problems or 0–1 integer linear programming (ILP). In these circuits, it was proven that maximizing dissipation is equivalent to maximizing gate output activity, appropriately weighted to account for differing load capacitances. The first problem in this work deals with identifying an input vector pair that maximizes the weighted circuit activity. In the second application we attempt to find an estimate for the maximum power-up current in circuits where power cut-off or gating techniques are used to reduce leakage current. Both problems were successfully formulated as SAT problems. SAT-Based and generic Integer Linear Programming (ILP) solvers are then used to find a solution. The experimental results obtained on a large number of benchmark circuits provide promising evidence that the proposed complete approach is both viable and useful and outperforms the random approach.

Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits

This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reduction in the number of test vectors required to detect faults in VLSI circuits. The algorithm is based on the circuit's maximum primary input cone size ( N) and minimum fanout ( F) values to decide the location and number of partitions. Particle swarm optimization (PSO) is used to determine the optimal values of N and F to minimize the number of test vectors, the number of partitions, and the increase in critical path delay due to the added partitions. The proposed algorithm has been applied to the ISCAS’85 benchmark circuits and the results are compared to other partitioning approaches, showing that the PSO partitioning algorithm produces similar results, approximately one-order of magnitude faster.

Specific Features of Faults of Combinational CMOS Circuits

This research work investigated a problem of application of transistors level fault model and its adequacy to faults at logical level of circuit. There were elaborated the faults at logical and at functional level using the software package CADENCE. The faults at transistors level were simulated by software package PSPICE. There were done the comparative results of fault simulation and fault coverage at transistors level and at logical level of CMOS circuit. Ill. 3, bibl. 4 (in English; summaries in English, Russian and Lithuanian,).

High-level current macro model for logic blocks

The authors present a frequency domain current macro-modeling technique for capturing the dependence of the block current waveform on its input vectors. The macro model is based on estimating the discrete cosine transform (DCT) of the current waveform and then taking the inverse transform to estimate the time domain current waveform. The DCT of a current waveform is very regular and closely resembles the DCT of a triangular or a trapezoidal wave. The authors use this fact and the relation between the DCT, discrete Fourier transform (DFT), discrete time Fourier transform (DTFT), and the Fourier transform (FT) to infer the template functions for the current macro model. These template functions are characterized by using various parameters like amplitude, phase decay factor, time period, etc. These parameters are modeled as functions of the input vector pair using regression. Regression is done on a set of current waveforms generated for each circuit using HSPICE. These template functions are used in an automatic characterization process to generate current macro models for various CMOS combinational circuits.

Effectiveness of very low voltage testing of bridging defects

Low supply voltage testing has traditionally been reported as an advantageous technique in detecting resistive bridging defects in combinational CMOS circuits. However, under certain topological conditions, the opposite effect is observed. These conditions are analysed. Applicability to diagnosis of bridging defects is discussed.

Design of quaternary logic systems and circuits

The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.

Model for Transient Fault Susceptibility of Combinational Circuits

Transient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.