Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits

Abstract

This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reduction in the number of test vectors required to detect faults in VLSI circuits. The algorithm is based on the circuit's maximum primary input cone size ( N) and minimum fanout ( F) values to decide the location and number of partitions. Particle swarm optimization (PSO) is used to determine the optimal values of N and F to minimize the number of test vectors, the number of partitions, and the increase in critical path delay due to the added partitions. The proposed algorithm has been applied to the ISCAS’85 benchmark circuits and the results are compared to other partitioning approaches, showing that the PSO partitioning algorithm produces similar results, approximately one-order of magnitude faster.