Abstract
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reduction in the number of test vectors required to detect faults in VLSI circuits. The algorithm is based on the circuit's maximum primary input cone size ( N) and minimum fanout ( F) values to decide the location and number of partitions. Particle swarm optimization (PSO) is used to determine the optimal values of N and F to minimize the number of test vectors, the number of partitions, and the increase in critical path delay due to the added partitions. The proposed algorithm has been applied to the ISCAS’85 benchmark circuits and the results are compared to other partitioning approaches, showing that the PSO partitioning algorithm produces similar results, approximately one-order of magnitude faster.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Engineering Applications of Artificial Intelligence
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
