CMOS Cell Research Articles

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This paper presents a localization system based on the use of electric compass and tracking IR light source. Digital RGB(Red, Green, Blue)signal of digital CMOS Camera is sent to CPLD which converts the color image to binary image at 30 frames per second. CMOS camera has IR filter and UV filter in front of CMOS cell. The filters cut off above 720nm light source. Binary output data of CPLD is sent to DSP that rapidly tracks the IR light source by moving Camera tilt DC motor. At a robot toward north, electric compass signals and IR light source angles which are used for calculating the data of the location system. Because geomagnetic field is linear in local position, this location system is possible. Finally, it is shown that position error is within <TEX>${\pm}1.3cm$</TEX> in this system.

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style

In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.

Design of a high performance self-timed ARM9 processor

This paper presents an asynchronous implementation of ARM9 processor, AEM32. We introduce an adaptive pipeline structure that makes the pipeline depth dynamically. We employ a parallel processing control based on datapath splitting to execute the instruction fed into the pipeline in parallel when they have different datapath. AEM32 is synthesized using a 0.35-µm CMOS cell library. Simulation results show that our implementation had 2.6 times higher performance than the asynchronous counterpart, AMULET3i. In terms of Et2, AEM32 shows 3 times higher efficiency than the other counterpart, ARM966HS.

RF CMOS Device Modelling for on Chip EMC Evaluation

In this work a SOC (System On Chip) design methodology, considering electromagnetic compatibility (EMC) is proposed. High frequency CMOS device models have been revised and adapted to the conditions required by a particular SoC chip. RF simulations were carried out in analog and digital SoĆs CMOS cells, using these models, including electromagnetic interference.

A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications

This work presents an efficient architecture design for deblocking filter in H.264/AVC using a novel fast-deblocking boundary-strength (FDBS) technique. Based on the FDBS technique, the proposed architecture divides the deblocking process into three filtering modes, namely offset-based, standard-based and diagonal-based filtering modes, to reduce the blocking artifact and improve the video quality in H.264/AVC. The proposed architecture is designed in Verilog HDL, simulated with Quartus II and synthesized using 0.18 μm CMOS cells library with the Synopsys Design Compiler. Simulation results demonstrate good performance in PSNR improvement and bit-rate reduction. Additionally, verification results through physical chip design reveal that the proposed architecture design can support 1,280?×?720@30 Hz processing throughput while clocking at 100 MHz. Comparisons with other studies show the excellent properties of the proposed architecture in terms of gate count, memory size and clock-cycle/macroblock.

Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs

A novel mechanism that flexibly adapts data flows and configures computational units is proposed to establish an application-specific data path in the digital signal processor (DSP) that can efficiently perform multistandard video codecs. Based on this mechanism, the proposed application-specific data path, using the very long instruction word (VLIW) architecture with eight computational units of five arithmetic logic units (ALUs), one multiplier and two load/store units, is designed to perform five adaptive operations according to the characteristics of the low-level functions of MPEG-2, MPEG-4 and H.264/AVC video codecs. Using these adaptive operations, the proposed application-specific data path reduces the number of clock cycles required by the TI TMS320C64x data path to perform the low-level functions of the MPEG-2 video encoder and the H.264/AVC video decoder by 23.10% and 28.43%, respectively, for 30 352times288-pixel Foreman frames. Additionally, considering the operating frequency, the proposed application-specific data path reduces the computation time required by the TI TMS320C64x data path to realize the abovementioned encoder and decoder by 19.86% and 25.41%, respectively. Based on the TSMC 0.18-mum CMOS cell library, the proposed application-specific data path is implemented, and exhibits the highest ratio of computational power to hardware cost among all of the data paths associated with the conventional DSPs in implementing the low-level functions of video codecs

A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC

In this paper, we present a VLSI design of transport processor for an AVS HDTV decoder SoC. The design provides a flexible data flow, which supports both broadcasting service and IPTV service with DVR capability. The design is characterized by two-bus architecture, in which a RISC CPU is used for control of general purpose and some dedicated hardware for accelerating data processing. The common on-chip SRAM is used to store input transport packets and the intermediate result in order to improve system performance and reduce the area. The design is described in Verilog HDL, simulated with VCS simulator, and implemented using 0.18 mum CMOS cell library. The circuit costs about 75 k equivalent logic gates and the processing capability is up to 90 Mbps

Algorithmic and architectural co-design for integer motion estimation of AVS

The video part of A VS has been finalized, in order to enhance coding performance. AVS video standard adopts some new features for motion estimation, such as variable block size search, multiple reference frames, and motion vector prediction. However, the better performance comes at the price of high computational complexity, data dependence and memory access requirement. These new features also make the hardware implementation more difficult, especially for real-time applications. In this paper, we firstly propose an integer motion estimation algorithm from hardware-oriented viewpoint. Experimental results show that the proposed algorithm has almost the same performance as the reference software of AVS in SDTV applications. Then the corresponding VLSI architecture is presented. The VLSI architecture has been described in Verilog HDL and synthesized using 0.18 mum Artisan CMOS cells library. The circuit totally costs about 400 K equivalent logic gates. At 108 MHz working frequency, the circuit can meet the real-time requirement for SDTV (720times576, 25 fps) applications, with the search area of 192times192. The co-design obtains better tradeoff between performance and gate-count

An efficient VLSI architecture of VLD for AVS HDTV decoder

In this paper, we present a VLSI design of variable length code decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode fixed length code, unsigned or signed k-th Exp-Golomb code, and AVS 2-D variable length code. Furthermore, it has a pre-processing submodule, which can perform start code detection and de-stuffing for the input bitstream. The proposed architecture has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18 /spl mu/ Artisan CMOS cells library by synopsys design compiler. The circuit costs about 15k equivalent logic gates (not including 4 kb on-chip SRAM). And the critical path is less than 6 ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, which can support real-time decoding for NTSC, PAL, 720p 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS video standard, it can be easily adapted to other coding standards.

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. In addition, the experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method. Our hierarchical approach reduces the runtimes drastically. Although this approach has possibility to generate wider placements than that of the flat approach, the experimental results show that the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach.

The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning

This paper presents a long length discrete Hartley transform (DHT) design with a new hardware efficient distributed arithmetic (DA) approach. The new DA design approach not only explores the constant property of coefficients as the conventional DA, but also exploits its cyclic property. To efficiently apply this approach to long length DHT, we first decompose the long length DHT algorithm to short ones using the prime factor algorithm (PFA), and further reformulate it by using Agarwal-Cooley algorithm such that all the partitioned short DHT still consists of the cyclic property. Besides, we also exploit the scheme of computation sharing on the content of ROM to reduce the hardware cost with the trade-off in slowing down the computing speeds. Comparing with the existing designs shows that the proposed design can reduce the area-delay product from 52% to 91% according to a 0.35 /an CMOS cell library.

A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits

Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes.

Distributed arithmetic realisation of cyclic convolution and its DFT application

The authors present a new hardware-efficient group distributed arithmetic (GDA) design approach for the one-dimensional (1-D) discrete Fourier transform (DFT). The approach adopts distributed arithmetic (DA) computation and exploits the good features of cyclic convolution to facilitate an efficient realisation of the 1-D N-point DFT using small ROM modules, a barrel shifter, and N accumulators. The proposed GDA design is achieved by rearranging the contents of the ROM into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DFT outputs to increase ROM utilisation. Moreover, combining the symmetrical property of the DFT coefficients with the proposed GDA design requires only half the ROM contents to be stored, which further reduces ROM size by a factor of two. Realisation of a long-length DFT formulated in cyclic convolution is based on data permutation of the rows and columns in the matrix to directly partition the long-length cyclic convolution into short ones, so that short length DFTs may be realised efficiently by the proposed GDA design to achieve low hardware cost. This design approach is termed the ‘block-based group distributed arithmetic approach’. Compared with existing systolic array designs and DA-based designs, the proposed GDA design can reduce the delay–area product by 29%–68% based on a 0.35 μm CMOS cell library.

Design-space exploration of the most widely used cryptography algorithms

Network data are, currently, often encrypted at a low level. In addition, as it is widely supported, the majority of future networks will use low-layer (IP level) encryption. Moreover, current trends imply that future networks are likely to be dominated by mobile terminals, thus, the power consumption and electromagnetic emissions aspects of encryption devices will be critical. This paper presents several realizations of the two most widely used encryption algorithms, DES and AES, both in software and in hardware. We present software implementations of the algorithms running on two of the state-of-the-art Intel IXP Network Processors and 11 hardware realizations based on a standard-cell library. In particular, five of our hardware realizations are conventional flip-flop based clocked designs, whereas the other six are either asynchronous, or latch-based synchronous designs. We demonstrate that the most efficient realization of the DES algorithm is one of the proposed asynchronous hardware implementations, whereas for the AES algorithm the latch-based design presented seems to be optimal. By placing and routing those designs, we have also realized that the commercial ASIC synthesis tools cannot accurately predict the area and the performance of the placed and routed final netlist in such designs, since the ASIC implementations of the encrypted algorithms include a very large number of wires and a limited number of logic CMOS cells.

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits

Due to device and voltage scaling scenarios for present and future deep-submicron CMOS technologies, it is inevitable that the off-state current (I/sub off/) of MOSFET transistors increases as the technology minimum dimensions scale down. Experimental evidence shows that the leakage current distribution of modern deep-submicron designs not only has a higher mean value but it also presents a larger variability as well. In this paper, we investigate the impact of threshold voltage mismatch as one plausible source for this increased variability. In digital circuit design, it is commonly assumed that the threshold voltage difference (mismatch) of static CMOS cells is negligible. However, threshold voltage mismatch (/spl Delta/V/sub to/) has a two-sided effect on the off-state current. Namely, the total cell's current can increase or decrease depending upon the direction of the V/sub t/ mismatch shift. This effect can be so severe that I/sub off/ can increase by more than one order of magnitude with respect to its nominal value due only to V/sub to/ mismatch. We further show through experimental results that the V/sub to/ mismatch of paired transistors working in the subthreshold regime can be worse by a factor of two as compared to transistors working in the saturation or linear regions. A factor of two larger spread is obviously quite devastating in terms of area, speed, and power consumption, should it be desired to attain the same I/sub off/ level as for a V/sub to/ mismatch characterized out of the subthreshold regime.

An efficient DMT modem for the G.LITE ADSL transceiver

In this paper, a discrete multitone (DMT) modem for the client side G.LITE ADSL transceiver is presented. The DMT modem is one of the most computationally intensive parts in the transceiver. In the design, computational complexity and operational regularity were traded-off to decide suitable fast Fourier transform (FFT)/Inverse FFT and frequency-domain equalization (FEQ) algorithms. We used the radix-2 real FFT and the normalized LMS that guarantees an equal convergence per tone. Based on operational community between FFT and FEQ, a resource-shared design was implemented. Datapath of the DMT modem comprises one real multiplier and two real adders, which are connected in parallel and flexibly used under control. The designed modem has been coded in VHDL and synthesized with 0.35-/spl mu/m standard CMOS cell. Synthesis results exhibit that the proposed system can provide a cost-effective solution to asymmetric digital subscriber line devices owing to its small design area.

A Scalable Structure for a Multiplier and an Inversion Unit in GF(2m)

Elliptic curve cryptography (ECC) offers the highest security per bit among the known public key cryptosystems. The operation of ECC is based on the arithmetic of the finite field. This paper presents the design of a 193-bit finite field multiplier and an inversion unit based on a normal basis representation in which the inversion and the square operation units are easy to implement. This scalable multiplier can be constructed in a variable structure depending on the performance area trade-off. We implement it using Verilog HDL and a 0.35 µm CMOS cell library and verify the operation by simulation.

A Strategy for Rapid Mismatch Evaluation of Transient Characteristics of CMOS Analog Cells

A strategy is presented to evaluate the statistical means and standard deviations of the transient characteristics of CMOS analog cells. Based upon the Monte Carlo analysis of electrical simulations, this strategy follows a circuit-theory based approach achieving an important reduction on matrix ranges and consequently on the number of operations involved in the resolution of the circuit. The CPU time-consuming reduction is achieved also by saving information corresponding to the nominal transient analysis. We include comparative results for several CMOS cells showing the advantages of the proposed strategy.

Motion estimation using MSD-first processing

A new most-significant-digit-first (MSD-first) motion estimation (ME) algorithm based on online arithmetic is proposed in the paper, together with its associated architecture. High-performance ME architectures are crucial for high-quality video applications with high resolution and frame rate, such as HDTV, DVD-video recorders and digital camcorders. The proposed algorithm decomposes the summation of absolute difference (SAD) and the comparison operations of full search block matching (FSBM) into digit level. The digit-level comparisons are interleaved into the separated SAD operations to distinguish the motion vector (MV) as early as possible. It operates in the MSD-first manner and eliminates redundant operations for less significant digits, while still extracting the exact MV of the selected search algorithm. The authors also demonstrate the online arithmetic designs for SAD and comparison, which are two primitive operations in the proposed algorithm. The proposed method saves 47.4% to 64.3% SAD computations of FSBM. In the implementation, a 4×4 array processor of the proposed ME using online arithmetic has a 2.84 ns critical path and 1510 gates with 0.35 μm 1P4 M CMOS cell library. It supports 83 mega 4×4 block matching per second and also reduces the ME operations of other fast search algorithms.

Portable digital clock generator for digital signal processing applications

A fully integrated clock generator with behaviour similar to a PLL is proposed. A free-running ring oscillator is used as internal clock and the output clock is generated using two counters. The clock generator is described in synthesisable VHDL-code and can therefore easily be made from standard cells found in any commercial standard CMOS cell library.