Abstract
A strategy is presented to evaluate the statistical means and standard deviations of the transient characteristics of CMOS analog cells. Based upon the Monte Carlo analysis of electrical simulations, this strategy follows a circuit-theory based approach achieving an important reduction on matrix ranges and consequently on the number of operations involved in the resolution of the circuit. The CPU time-consuming reduction is achieved also by saving information corresponding to the nominal transient analysis. We include comparative results for several CMOS cells showing the advantages of the proposed strategy.
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