CMOS Application-specific Integrated Circuit Research Articles

Wearable and Noninvasive Device for Integral Congestive Heart Failure Management in the IoMT Paradigm.

Noninvasive remote monitoring of hemodynamic variables is essential in optimizing treatment opportunities and predicting rehospitalization in patients with congestive heart failure. The objective of this study is to develop a wearable bioimpedance-based device, which can provide continuous measurement of cardiac output and stroke volume, as well as other physiological parameters for a greater prognosis and prevention of congestive heart failure. The bioimpedance system, which is based on a robust and cost-effective measuring principle, was implemented in a CMOS application specific integrated circuit, and operates as the analog front-end of the device, which has been provided with a radio-frequency section for wireless communication. The operating parameters of the proposed wearable device are remotely configured through a graphical user interface to measure the magnitude and the phase of complex impedances over a bandwidth of 1 kHz to 1 MHz. As a result of this study, a cardiac activity monitor was implemented, and its accuracy was evaluated in 33 patients with different heart diseases, ages, and genders. The proposed device was compared with a well-established technique such as Doppler echocardiography, and the results showed that the two instruments are clinically equivalent.

Petabit-Scale Silicon Photonic Interconnects With Integrated Kerr Frequency Combs

Silicon photonics holds significant promise in revolutionizing optical interconnects in data centers and high performance computers to enable scaling into the Pb/s package escape bandwidth regime while consuming orders of magnitude less energy per bit than current solutions. In this work, we review recent progress in silicon photonic interconnects leveraging chip-scale Kerr frequency comb sources and provide a comprehensive overview of massively scalable silicon photonic systems capable of capitalizing on the large number of wavelengths provided by such combs. We first consider the high-level architectural constraints and then proceed to detail the corresponding fundamental device designs supported by both simulated and experimental results. Furthermore, the majority of experimentally measured devices were fabricated in a commercial 300 mm foundry, showing a clear path to volume manufacturing. Finally, we present various system-level experiments which illustrate successful proof-of-principle operation, including flip-chip integration with a co-designed CMOS application-specific integrated circuit (ASIC) to realize a complete Kerr comb-driven electronic-photonic engine. These results provide a viable and appealing path towards future co-packaged silicon photonic interconnects with aggregate per-fiber bandwidth above 1 Tb/s, energy consumption below 1 pJ/bit, and areal bandwidth density greater than 5 Tb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The first family of application-specific integrated circuits for programmable and reconfigurable metasurfaces

Reconfigurable metasurfaces are man-made surfaces, which consist of sub-wavelength periodic elements—meta-atoms—that can be reconfigured to manipulate incoming electromagnetic waves. However, reconfigurable metasurfaces developed to-date, have limitations in terms of loading impedance range, reconfiguration delay and power consumption. Also, these systems are costly and they require bulky electronics and complex control circuits, which makes them unattractive for commercial use. Here, we report the first family of CMOS application-specific integrated circuits that enable microsecond and microwatt reconfiguration of complex impedances at microwave frequencies. Our approach utilizes asynchronous digital control circuitry with chip-to-chip communication capabilities, allowing simple and fast reconfiguration via digital devices and user-friendly software. Our solution is low-cost and can cover arbitrary board-to-board metasurfaces, with different sizes and shapes.

Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction

Objective. Design a novel architecture for real-time quantitative characterization of functional brain connectivity (FC) networks derived from wearable electroencephalogram (EEG). Approach. We performed an algorithm to architecture mapping for the calculation of phase lag index to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. This mapping was optimized using approximations in the mathematical definitions of the algorithms which reduce its computational complexity and produce a more hardware amenable implementation. Main results. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131 µs, utilizes 71% of the total logic resources in the FPGA, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937 K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS application specific integrated circuit technology. Significance. The proposed architecture can calculate the FC and extract the graph-theoretic parameters in real-time with low power consumption. This characteristic makes the architecture ideal for applications such as a wearable closed-loop neurofeedback systems, where constant monitoring of the brain activity and fast processing of EEG is necessary to control the appropriate feedback.

A 354 Mb/s 0.37 mm2 151 mW 32-User 256-QAM Near-MAP Soft-Input Soft-Output Massive MU-MIMO Data Detector in 28nm CMOS

This letter presents a novel data detector application-specific integrated circuit (ASIC) for massive multiuser multiple-input multiple-output (MU-MIMO) wireless systems. The ASIC implements a modified version of the large-MIMO approximate message passing algorithm (LAMA), which achieves near-optimal error-rate performance (i) under realistic channel conditions and (ii) for systems with as many users as base-station (BS) antennas. The hardware architecture supports 32 users transmitting up to 256-QAM simultaneously and in the same frequency band, and provides soft-input soft-output capabilities for iterative detection and decoding. The fabricated 28nm CMOS ASIC occupies 0.37 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieves a throughput of 354 Mb/s, consumes 151 mW, and improves the SNR by more than 11 dB compared to existing data detectors in systems with 32 BS antennas and 32 users for realistic wireless channels. In addition, the ASIC achieves $4\boldsymbol \times $ higher throughput per area than a recently proposed message-passing detector.

(Invited) The New Silicon Industry: Silicon CMOS ASICs Incorporating Compound Semiconductors

Computation has defined technology leadership in the silicon industry, driving development from bipolars to MOS to CMOS and finally incorporating adaptions like strained Si to continue effective scaling. The previous world of application specific integrated circuits (ASICs) has been largely absorbed into dense digital die with software defining application. As end markets demand IC innovation for product differentiation, de-integration of silicon systems is occurring, as leading edge CMOS nodes for intense computation are not optimized for communication, photonics, or power management. Silicon ICs incorporating III-V LEDs and HEMTs into their design will usher in a new age of high growth ASICs in a variety of different applications.

(Invited) The New Silicon Industry: Silicon CMOS ASICs Incorporating Compound Semiconductors

We describe the integration of new semiconductor materials into a silicon CMOS process utilizing the existing silicon CMOS supply chain. Epitaxy, wafer bonding, device modeling and design incorporate new innovative elements, allowing for a scalable commercial model. First applications will occur in application-specific integrated circuits (ASICs), as was the case with conventional silicon integration at the start of the industry.

An Analog Front End ASIC for Cardiac Electrical Impedance Tomography.

In this paper, an end-to-end CMOS application specific integrated circuit (ASIC) for readout channel in a cardiac electrical impedance tomography system is presented. The ASIC consists of an integrated current driver for current injection, an instrumentation amplifier, variable gain amplifier at the analog front end for voltage readout from electrodes, and an on-chip 10-bit successive approximation register analog to digital converter with serial peripheral interface. The ASIC is fabricated in the CMOS 0.18 $\mu$ m process with a supply voltage of 3.3 V. Amplitude and phase extraction of the voltages is performed in the digital domain with a matched filter. A fully integrated solution for use in multiple electrode system is demonstrated. The readout chain in the ASIC achieves a minimum signal-to-noise ratio of 71dB over the frequency range of 500 Hz-700 kHz, while maintaining an average accuracy of 99.7 $\%$. Frame rates of 21 frames per second for a 32 electrode system is feasible, and the ASIC has an overall power consumption of 11.8 mW.

High Density, High Radiance $\mu$ LED Matrix for Optogenetic Retinal Prostheses and Planar Neural Stimulation.

Optical neuron stimulation arrays are important for both in-vitro biology and retinal prosthetic biomedical applications. Hence, in this work, we present an 8100 pixel high radiance photonic stimulator. The chip module vertically combines custom made gallium nitride μ LEDs with a CMOS application specific integrated circuit. This is designed with active pixels to ensure random access and to allow continuous illumination of all required pixels. The μLEDs have been assembled on the chip using a solder ball flip-chip bonding technique which has allowed for reliable and repeatable manufacture. We have evaluated the performance of the matrix by measuring the different factors including the static, dynamic power consumption, the illumination, and the current consumption by each LED. We show that the power consumption is within a range suitable for portable use. Finally, the thermal behavior of the matrix is monitored and the matrix proved to be thermally stable.

High‐performance elliptic curve cryptography processor over NIST prime fields

This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high-performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards and Technology standard. A novel combined point doubling and point addition architecture is proposed using efficient modular arithmetic to achieve high speed and low hardware utilisation of the ECP in Jacobian coordinates. This new architecture has been synthesised both in application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA). A 65 nm CMOS ASIC implementation of the proposed ECP in Jacobian coordinates takes between 0.56 and 0.73 ms for 224-bit and 256-bit elliptic curve cryptography, respectively. The ECSM is also implemented in an FPGA and provides a better delay performance than previous designs. The implemented design is area-efficient and this means that it requires not many resources, without any digital signal processing (DSP) slices, on an FPGA. Moreover, the area–delay product of this design is very low compared with similar designs. To the best of the authors’ knowledge, the ECP proposed in this study over F p performs better than available hardware in terms of area and timing.

On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

Many recent advances in sparse coding led its wide adoption in signal processing, pattern classification, and object recognition applications. Even with improved performance in state-of-the-art algorithms and the hardware platform of CPUs/GPUs, solving a sparse coding problem still requires expensive computations, making real-time large-scale learning a very challenging problem. In this paper, we cooptimize algorithm, architecture, circuit, and device for real-time energy-efficient on-chip hardware acceleration of sparse coding. The principle of hardware acceleration is to recognize the properties of learning algorithms, which involve many parallel operations of data fetch and matrix/vector multiplication/addition. Today's von Neumann architecture, however, is not suitable for such parallelization, due to the separation of memory and the computing unit that makes sequential operations inevitable. Such principle drives both the selection of algorithms and the design evolution from CPU to CMOS application-specific integrated circuits (ASIC) to parallel architecture with resistive crosspoint array (PARCA) that we propose. The CMOS ASIC scheme implements sparse coding with SRAM dictionaries and all-digital circuits, and PARCA employs resistive-RAM dictionaries with special read and write circuits. We show that 65 nm implementation of the CMOS ASIC and PARCA scheme accelerates sparse coding computation by $394$ and $2140\times$ , respectively, compared to software running on a eight-core CPU. Simulated power for both hardware schemes lie in the milli-Watt range, making it viable for portable single-chip learning applications.

A Bulk-Micromachined Three-Axis Capacitive MEMS Accelerometer on a Single Die

This paper presents a high-performance three-axis capacitive microelectromechanical system (MEMS) accelerometer implemented by fabricating individual lateral and vertical differential accelerometers in the same die. The fabrication process is based on the formation of a glass-silicon-glass multi-stack. First, a 35- $\mu \text{m}$ thick $\langle 111\rangle $ silicon structural layer of an Silicon-On-Insulator (SOI) wafer is patterned with deep reactive ion etching (DRIE) and attached on a base glass substrate with anodic bonding, whose handle layer is later removed. Next, the second glass wafer is placed on the top of the structure not only for allowing to implement a top electrode for the vertical accelerometer, but also for acting as an inherent cap for the entire structure. The fabricated three-axis MEMS capacitive accelerometer die measures $12\,\times \,7\,\times \,1$ mm3. The $x$ -axis and $y$ -axis accelerometers demonstrate measured noise floors and bias instabilities equal to or better than 5.5 $\mu \text{g}/\surd $ Hz and 2.2 $\mu \text{g}$ , respectively, while the $z$ -axis accelerometer demonstrates $12.6~\mu \text{g}/\surd $ Hz noise floor and $17.4~\mu \text{g}$ bias instability values using hybrid-connected fourth-order sigma–delta CMOS application specific integrated circuit (ASIC) chips. These low noise performances are achieved with a measurement range of over ±10 g for the $x$ -axis and $y$ -axis accelerometers and +12/−7.5 g for the $z$ -axis accelerometer, suggesting their potential use in navigation grade applications. [2014-0351]

A Monolithic Segmented Germanium Detector with Highly Integrated Readout

We have constructed a pixelated germanium detector using a technique which has been shown to provide good isolation between adjacent pixels. In this work we present initial tests of the application of a low-noise CMOS ASIC to read out this detector. The detector has 64 pixels, each 0.5 mm×5 mm, arranged as a series of strips. It is connected by wire-bonds to two 32-channel application-specific integrated circuits (ASICs) which provide a complete photon-counting chain for every channel. Since the size of the pixel array is no longer restricted by the difficulties of instrumenting large channel-count conventional electronics, this development will open up the possibility of even larger arrays, similar to those offered by silicon detectors.

A low-power CMOS ASIC for X-ray Silicon Drift Detectors low-noise pulse processing

We present an Application Specific Integrated Circuit (ASIC), named VEGA-1, designed and manufactured for low-power analog pulse processing of signals from Silicon Drift Detectors (SDDs). The VEGA-1 ASIC consists of an analog and a digital/mixed-signal section to achieve all the functionalities and specifications required for high-resolution X-ray spectroscopy in the energy range from 500 eV to 60 keV with low power consumption. The VEGA-1 ASIC has been designed and manufactured in 0.35-μm CMOS mixed-signal technology in single and 32-channel version with dimensions of 200 μm × 500 μm per channel. A minimum intrinsic ENC of 12 electrons r.m.s. at 3.6 μs shaping time and room temperature is measured for the ASIC without detector. The VEGA-1 has been tested with Q10-SDD designed in Trieste and fabricated at FBK, with an active area of 10 mm2 and a thickness of 450 μm. The aforementioned detector has an anode current of about 180 pA at +22°C. A minimum Equivalent Noise Charge (ENC) of 16 electrons r.m.s. at 3.0 μs shaping time and −30°C has been demonstrated with a total measured power consumption of 482 μW.

A photon-counting silicon-strip detector for digital mammography with an ultrafast 0.18-μm CMOS ASIC

We have evaluated a silicon-strip detector with a 0.18-μm CMOS application specific integrated circuits (ASIC) containing 160 channels for use in photon-counting digital mammography. Measurements were performed at the Elettra light source using monochromatic X-ray beams with different energies and intensities. Energy resolution, ΔE/Ein, was measured to vary between 0.10 and 0.23 in the energy range of 15–40keV. Pulse pileup has shown little effect on energy resolution.

Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm

Soft-output detection of a multiple-input-multiple-output (MIMO) signal pose a significant challenge in future wireless systems. In this paper, we introduce a soft-output modified metric first (MMF)-LSD algorithm for MIMO detection. We design a scalable architecture and address a method to decrease memory requirements. We provide implementation results for a spatial multiplexing (SM) system with four transmitted streams and with 16- and 64-quadrature amplitude modulation (QAM) on a 0.18-μ m CMOS application specific integrated circuit (ASIC) technology. The MFF-LSD implementation is more efficient than the depth first (DF)-LSD in the crucial low signal-to-noise rate (SNR) region and the detection rate of the 64-QAM implementation is 39.2 Mbps@26 db with 48.2 kGEs complexity.

Femtosecond Radiation Experiment Detector for X-Ray Free-Electron Laser (XFEL) Coherent X-Ray Imaging

A pixel array detector (PAD) module has been developed at Cornell University for the collection of diffuse diffraction data in anticipation of coherent X-ray imaging experiments that will be conducted at the Linac Coherent Light Source (LCLS) at the SLAC National Accelerator Laboratory. The detector is designed to collect X-rays scattered from monochromatic femtosecond pulses produced by the LCLS X-ray laser at framing rates up to 120 Hz. Because X-rays will arrive on femtosecond time scales, the detector must be able to deal with instantaneous count-rates in excess of 1017 photons per second per pixel. A low-noise integrating front-end allows the detector to simultaneously distinguish single photon events in low-flux regions of the diffraction pattern, while recording up to several thousand X-rays per pixel in more intense regions. The detector features a per-pixel programmable two-level gain control that can be used to create an arbitrary 2-D, two-level gain pattern across the detector; massively parallel 14-bit in-pixel digitization; and frame rates in excess of 120 Hz. The first full-scale detector will be 1516 x 1516 pixels with a pixel size of 110 X 110 microns made by tiling CMOS ASICs (Application Specific Integrated Circuits) that are bump-bonded to high-resistivity silicon diodes. X-ray testing data of the first 185 X 194 pixel bump-bonded ASICs is presented. These are tiled to make the final detector. The measurements presented include confirmation of single photon sensitivity, pixel response profiles indicating a nearly single-pixel point spread function, radiation damage measurements and noise performance.

High-resolution UV, alpha and neutron imaging with the Timepix CMOS readout

A CMOS application-specific integrated circuit (ASIC) called the “Timepix” has been used to readout the pulsed charge signal from various microchannel plate (MCP) stacks. The Timepix 256×256 array is a newer version of the Medipix2 ASIC with added features and modes. One of these modes is the “time over threshold” (TOT) mode where the amplitude of a single charge event can be determined per pixel. With a properly sized input charge cloud from an MCP stack, the centroid of the charge cloud can be determined to sub-pixel accuracy, allowing much higher spatial resolution than the 55 μm pixel size. Using this technique, we demonstrate a spatial resolution better than 57 lp/mm for UV photons, limited by the MCP pore spacing. Also, by changing the top MCP in the stack to a neutron-sensitive MCP, we show a spatial resolution to thermal neutrons of less than 35 μm FWHM. This technique can also be applied to alpha particle imaging using silicon diode arrays bump bonded to a Timepix. Allowing the large conversion charge generated by the alpha particle to diffuse over many pixels, we can centroid 5.5 MeV alphas from 241Am to 18 μm FWHM.

A thermal van der Pauw test structure

A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The microstructure was fabricated using a commercial CMOS application-specific integrated circuit process followed by anisotropic silicon etching. It consists of a cross-shaped sandwich of the dielectric CMOS layers isolated from the bulk silicon by four narrow suspension arms. Integrated polysilicon resistors make it possible to generate controlled amounts of heat power and to measure local temperature changes to determine the thermal response of the structure. The measurement principle exploits the analogy between the two-dimensional (2-D) heat flow in thin film samples and the electrical current pattern in thin film conductors. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of the dielectric CMOS layers. This resistance is equivalent to an average in-plane thermal conductivity of the dielectric layer sandwich of /spl kappa/=1.44 W m/sup -1/ K/sup -1/. Thermal finite element simulations showed that the radiative heat loss from the structure has a negligible effect on the extracted /spl kappa/ value.

Single event upset test structures for digital CMOS application specific integrated circuits

A test structure methodology for digital CMOS ASICs (application-specific integrated circuits) that can be used to evaluate the hardness of various ASIC libraries and processes is described. The method identifies categories of ASIC cells and uses a select set of worst-case test structures to obtain the parameters necessary to evaluate a library and process, and make a tractable, bounded estimate of the expected chip hardness. In addition, if the error rates prove to be excessive, this method helps identify the cells in which hardening efforts will be most productive. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU (single event upset) response and designing a structure to characterize each response for each category. These methods are being applied in the development of ASIC options for hardened chip design and have already been used to design an SEU hardened ASIC controller. >