CMOS Application-specific Integrated Circuit Research Articles

5 V compatibility with 3.3 V-only CMOS ASICs

A 3.3 V-only CMOS I/O buffer is proposed that interfaces with 5 V CMOS and TTL devices. This new buffer eliminates the 5 V power supply bus on the application specific integrated circuit (ASIC) chip while greatly improving the performance and reliability of the I/O buffer. In addition, the cost of packaging these ASICs is reduced due to removing the need of supporting a 5 V power plane on the package. The interfacing issues and the characteristics of the proposed I/O buffer are examined in detail.

A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips

A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8- mu m, four-level-metal, single-poly CMOS process, with a 0.45- mu m nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip. >

Low-cost testing of high-density logic components

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Boundary-scan design principles for efficient LSSD ASIC testing

A boundary-scan logic design method that depends only on level-sensitive scan design (LSSD) principles has been developed for IBM CMOS application-specific integrated circuit (ASIC) products. This technique permits comprehensive testing of LSSD ASICs with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic test equipment (ATE). This paper describes the LSSD logic structures required, the reduced-pin-count testing and burn-in processes used, and the ASIC product design decisions that must be made to establish a consistent boundary-scan implementation.

Application and evaluation of direct-write electron beam for ASICs

The application of direct-write electron-beam (DW-EB) technology to 1.3- mu m fine geometry and high-density 24 K-gate CMOS VLSI is investigated. Particular attention is paid to EB radiation damage of MOS devices and the effectiveness of DW-EB for CMOS application-specific integrated circuit (ASIC) VLSIs. To increase throughput for direct-writing and maintain good resolution, a high-sensitivity EB resist and appropriate proximity-effect correction method are adopted. EB radiation damage cannot be observed when low-electron beam dosage is applied to thin 25- mu m oxide lightly doped drain (LDD) structure devices, thus making DW-EB applicable for fabricating CMOS VLSIs. Good electrical characteristics, high reliability and good yield can also be obtained. The advantages of DW-EB for quick turnaround time and more efficient debugging capability by forming different VLSIs on the same wafer are discussed. >