Abstract
A 3.3 V-only CMOS I/O buffer is proposed that interfaces with 5 V CMOS and TTL devices. This new buffer eliminates the 5 V power supply bus on the application specific integrated circuit (ASIC) chip while greatly improving the performance and reliability of the I/O buffer. In addition, the cost of packaging these ASICs is reduced due to removing the need of supporting a 5 V power plane on the package. The interfacing issues and the characteristics of the proposed I/O buffer are examined in detail.
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