A thermal van der Pauw test structure

Abstract

A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The microstructure was fabricated using a commercial CMOS application-specific integrated circuit process followed by anisotropic silicon etching. It consists of a cross-shaped sandwich of the dielectric CMOS layers isolated from the bulk silicon by four narrow suspension arms. Integrated polysilicon resistors make it possible to generate controlled amounts of heat power and to measure local temperature changes to determine the thermal response of the structure. The measurement principle exploits the analogy between the two-dimensional (2-D) heat flow in thin film samples and the electrical current pattern in thin film conductors. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of the dielectric CMOS layers. This resistance is equivalent to an average in-plane thermal conductivity of the dielectric layer sandwich of /spl kappa/=1.44 W m/sup -1/ K/sup -1/. Thermal finite element simulations showed that the radiative heat loss from the structure has a negligible effect on the extracted /spl kappa/ value.