Analog CMOS Circuits Research Articles

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation between the ratio of the transconductance over DC drain current g/sub m//I/sub D/ and the normalized current I/sub D//(W/L). The g/sub m//I/sub D/ indeed is a universal characteristic of all the transistors belonging to a same process. It may be derived from experimental measurements and fitted with simple analytical models. The method was applied successfully to the design of a silicon-on-insulator (SOI) micropower operational transconductance amplifier (OTA).

A CMOS analog circuit for Gaussian functions

A simple CMOS analog circuit that performs the Gaussian function for classification applications is introduced. Combining the exponential characteristics of MOS transistors in weak inversion and the square characteristics in strong inversion the function is built. Design constraints and mismatch effects are discussed, as well as the layout optimization. The circuit has been designed in a SOI technology and manufactured. Good experimental results are obtained which shows that the circuit is suitable to be included as a building block of an IC to perform classification tasks or other possible applications.

CMOS analogue adder

A CMOS analogue circuit is proposed that computes the sum of two voltages. The circuit is self-biased, only requires a small number of transistors, and offers good accuracy over a wide range of input values. The design makes no special demands on device aspect ratios and could offer an economic alternative to conventional approaches. Simulation results have shown that total harmonic distortion (THD) is lower than –40 dB for output voltages up to 4 V peak to peak.

Optimum CMOS stack generation with analog constraints

An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described in this paper. The set of stacks obtained is optimum with respect to a cost function which accounts for critical parasitics and device area minimization. Device interleaving and common-centroid patterns are automatically introduced when possible, and all symmetry and matching constraints are enforced. The algorithm is based on operations performed on a graph representation of circuit connectivity, exploiting the equivalence between stack generation and path partitioning in the circuit graph. Path partitioning is carried out in two phases: in the first phase, all paths are generated by a dynamic programming procedure. In the second phase, the optimum partition is selected by solving a clique problem. Original heuristics have been introduced, which preserve the optimality of the solution, while effectively improving the computational efficiency of the algorithm. The algorithm has been implemented in the C programming language. Many test cases have been run, and the quality of results is comparable to that of hand-made circuits. Results also demonstrate the effectiveness of the heuristics employed, even for relatively complex circuits. >

Evaluation of the hot‐carrier‐induced offset voltage of differential pairs in analogue CMOS circuits

AbstractUsing a specifically developed measurement set‐up and a test structure typical for analogue applications, high precision measurements of the stress‐induced offset voltage degradation of differential pairs are presented. Extrapolation to operating conditions yields valuable information for analogue design in the sub‐micron CMOS regime.

Analog CMOS implementation of high frequency least-mean square error learning circuit

A continuous-time analog CMOS circuit with external feedback amplifiers implementing the least-mean square error adaptive learning algorithm has demonstrated a frequency of operation of 80 MHz, an adaptivity of 60 dB, a minimum notch width of 20 kHz, a minimum adapt time constant of 20 /spl mu/s, and the simultaneous cancellation of two continuous-wave (CW) interferers. Auto-zeroing is used to cancel multiplier and integrator offsets. A fully monolithic adaptive filter circuit was also realized.

A single poly EEPROM cell structure for use in standard CMOS processes

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a "floating gate". The inversion layer as "control node (gate)". Test chips which were fabricated in a 0.8 /spl mu/m/150 /spl Aring/ standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-/spl mu/m CMOS process with V/sub T/=/spl plusmn/0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV/sub ptp/ and a powerdrain of only 110 /spl mu/W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analog CMOS implementation of cellular neural networks

The analog CMOS circuit realization of cellular neural networks with transconductance elements is presented. This realization can be easily adapted to various types of applications in image processing just by choosing the appropriate transconductance parameters according to the predetermined coefficients. The effectiveness of the designed circuits for connected component detection is shown by HSPICE simulations. For fixed function cellular neural network circuits, the number of transistors is reduced further by using multi-input transconductance elements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Charge injection in current copier cells

The current copier cell [1] is a versatile building block increasingly used in many analogue CMOS circuits. However, charge injection, noise, Early effect and leakage current affect its accuracy. The Letter focuses on charge injection. A new model, derived from the work of Vittoz [2] and Sheu et al. [3], is presented to predict the actual partition of the injected charges. The results are compared with experimental measurements on a test circuit.

CMOS analog/digital circuit of the hysteresis McCulloch-Pitts neuron for Ramsey numbers

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCulloch-Pitts binary neuron found five Ramsey numbers. The analog CMOS sigmoid circuit with variable gain controls has been fabricated and tested using the SAC data acquisition board interfaced with a TMS 32010 processor. Hysteresis can be implemented by the positive feedback in the fabricated CMOS analog circuit.

CMOS selfbiased Euclidean distance computing circuit with high dynamic range

A CMOS analogue circuit is proposed that computes the Euclidean distance between two vectors whose coefficients are represented by currents. The circuit is selfbiased, requires only a small number of transistors, and offers good accuracy over a wide range of input values.

ANALOG CMOS NEURAL CIRCUITS — IN SITU LEARNING

This paper presents a tutorial review of artificial neurons and synapses which are implemented as analog CMOS circuits and which employ in situ learning of the synaptic weights. In situ learning implies that circuits local to the synapses perform computation of the weight updates according to built-in learning rules. This makes these synapses less flexible than those with external learning which do not commit to predetermined rules. On the other hand, in situ learning has potential advantages in increased learning rates in compensating for component inaccuracies and in adapting to nonstationary tasks. Both supervised and unsupervised learning rules and their implementations are described. The discussion focusses on synapses whose weights are stored on capacitors or in binary registers but also includes EEPROMs and CCDs. The emphasis is on synapses implemented using analog multipliers but other circuit techniques such as pulse streams are also briefly mentioned.

CMOS phase detector and four quadrant multiplier for implementation in analogue neural networks

Two analogue CMOS circuits for implementation in artificial neural networks are proposed. The phase detector is based on the nonsaturation region of operation of MOS transistors, and the multiplier on the square law characteristics of MOS devices. The multiplier accepts a pair of differential input voltages and can either generate a differential or a single-ended output. It has a measured linearity error of less than 0.5% for an X+ input pattern of 2.4 and 2.6 V. The phase detector maintains a phase error of less than 0.1%.

Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

AbstractA major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by fitted quadratic models and then use these computationally inexpensive models to optimize the parametric yield. In this paper quadratic statistical circuit performance models are applied to maximize the parametric yield of CMOS analogue circuits. It is found that quadratic polynomials may not always model the circuit performances well. However, with engineering knowledge applied to identify and reduce the causes of the errors, accurate performance models and yield maximization can be achieved with a reasonably small number of circuit simulations, as illustrated through examples. Distinctions between the present method and previous applications of quadratic modelling to statistical circuit design are made.

Analog CMOS synaptic learning circuits adapted from invertebrate biology

Analog CMOS circuits implementing abstractions of certain biological synaptic processes are presented. In particular, the circuits extract features of synaptic learning observed in the marine mollusk Aplysia. Two types of nonassociative learning, habituation and sensitization, as well as associative learning (classical conditioning), are modeled. The synaptic learning rules used by Aplysia are considerably more complex than those typically used in artificial neural networks (ANNs), leading to the speculation that additional biological detail may be beneficial in ANN models. The synaptic circuitry described is expected to be useful as a basic primitive in ANNs with higher order synapses and learning rules that perform temporal association of multiple inputs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CMOS mean field learning

Analogue CMOS circuits which implement constrastive Hebbian learning have been designed, fabricated, and tested. A 19 neuron, 342 synapse mean field network, or deterministic Boltzmann machine (4.16 × 2.76 mm2 in 1.2 μm CMOS) has been constructed based on these synaptic circuits. Very small learning step size may be employed in this chip, which is advantageous for reliable mean field learning.

Harmonic and intermodulation performance of analogue CMOS circuits owing to mobility reduction

The current-voltage characteristic of a MOSFET operating in the saturation region and including the effect of surface-channel mobility reduction is modelled by a third-order polynomial expression. Using this expression, a general expression is obtained for the harmonics and intermodulation performance of a MOSFET operating in saturation and excited by a multisinusoidal gate-to-source voltage. Using this expression, the second-harmonic and the thirdharmonic distortion performance of a linear voltage-to-current convertor proposed recently has been calculated. The results obtained are compared with previously published results

High-bandwidth CMOS test buffer with very small input capacitance

An analogue CMOS buffer configuration, which eliminates the tradeoff between high bandwidth and very low input capacitance, has been designed and simulated in a standard 2 μm process. The circuit shows a total input capacitance less than 50 fF up to 12 MHz and less than 110 fF overall with a 3 dB bandwidth of 20 MHz when driving a 15 pF and 100 kω load. The very small input capacitance and high bandwidth make the circuit very suitable for testing internal sensitive nodes in CMOS analog or mixed-mode circuits.

Silicon models of associative learning in Aplysia

Relatively simple invertebrate animals exhibit an impressive variety of learning and memory behaviour including such associative learning tasks as classical or Pavlovian conditioning. The cellular machinery responsible for this behaviour is beginning to be understood by neurophysiologists in certain well-studied species such as the marine mollusc Aplysia. We describe analog CMOS circuits which can be used to qualitatively mimic the mechanisms of associative learning in this creature. In particular we model the synaptic plasticity and activity-dependent facilitation in sensorimotor synapses responsible for classical conditioning of the gill withdrawal reflex. The same circuits implement the nonassociative learning mechanisms of habituation and sensitization. We also discuss considerations in abstracting from the biological mechanisms when developing artificial neural systems. The specific circuits for Aplysia described in this paper are suggestive of ways to implement VLSI area-efficient associative learning circuits in general, especially those which perform in situ temporal associations on multiple synaptic inputs.