CMOS 6T SRAM Research Articles

A SMART DESIGN OF A MULTI-DIMENSIONAL ANTENNA TO ENHANCE THE MAXIMUM SIGNAL CLUTCH TO THE ALLOWABLE STANDARDS IN 5G COMMUNICATION NETWORKS

At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell. Since the operating range of 5G communication networks is the same as that of the previous generation, there are no difficulties in using these antennas on 5G communication networks. For any technology, the use of antennas makes it possible to bring data rates closer to maximum values. The new technology that uses separate receivers and transmitters on the same frequency band has further increased the speed of receiving and transmitting data. The design of the existing 4G modem provides for the use of antenna technology. The proposed model provides the construction of a multidimensional antenna. The other passive devices it has a one-way direction, which increases the received signal and reduces the amount of interference from the sides to the back. Therefore, the proposed model possible to increase the signal level to acceptable values, even at unstable reception levels thereby increasing the speed of receiving and transmitting the information. The undoubted advantage of panel antennas is their low cost and exceptional reliability. There is practically nothing in the design that can be broken even when falling from a great height. The only weak point is the high-frequency cable, which can break at the point where it enters the case. To extend the life of the device, the cable must be securely connected.

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x \({10}^{-6 }\)A/µm with reduced OFF-state leakage current up to1.37 x \({10}^{-17 }\)A/µm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 and 400 K shows a small variation in OFF-state current (< 15 %). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All design and analysis have been done with a 2D/3D Visual TCAD device simulator.

Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistor (6T) and eight-transistor (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45× higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5× for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments.

Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology

&lt;p&gt;This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.&lt;/p&gt;

Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design

Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.

Impact of Single Event Upset on Voltage and Current Behaviors of CNTFET SRAM and a Comparison with CMOS SRAM

Carbon nanotubes (CNTs) provide a better alternative of silicon when it comes to nanoscales. Thanks to the high stability and high performance of carbon nanotube, CNT-based FET (CNTFET) devices are gaining popularity of late. They provide high packaging densities. Not much study had been done to analyze the characteristics of CNTFET SRAM in the presence of single event upset (SEU). The aim of this paper is to analyze the way in which SEU brings alterations in CNTFET SRAM characteristics and perform its comparison with respect to CMOS 6T SRAM. This paper analyzes the impact of SEU on voltage and current characteristics in CNTFET-based SRAM cell during three different conditions —read, write and hold modes. In the analysis, CNTFET SRAM showed that even small amount of radiations can cause flipping in cells and special circuitries are required to detect and correct the errors for SEU affected SRAM.

FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects

With shrinking dimensions and increased number of on-chip transistors radiation can provoke faults in integrated circuits even at sea level. This paper presents a comparison of fully depleted SOI (FDSOI) and Bulk CMOS 6T SRAM cells' resilience to radiation effects. Both cells were simulated using TCAD tools, considering heavy-ion impacts in different locations of the transistor as well as using different impact angles. Two types of radiation effects have been considered: Single-Event Transients (SETs) and Single-Event Upsets (SEUs). The minimum critical collected charge (CC) to flip a cell is almost the same in both technologies. However, it is shown that a FDSOI SRAM cell needs a heavy-ion impact with a Linear Energy Transfer (LET) around 10 times greater than a Bulk-CMOS SRAM cell, to generate a similar CC and to flip a cell.

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies

The impact of gate-oxide breakdown on SRAM stability

We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 /spl mu/A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown.

On the SiO/sub 2/-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology

This paper describes a leading-edge 0.13 /spl mu/m low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I/sub off/) and gate delay (T/sub d/) performance at operating voltages (V/sub cc/) of 1.5 V and 1.2 V, devices with 0.11 /spl mu/m nominal gate length (L/sub g-nom/) and various gate-oxide thicknesses (T/sub ox/) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 /spl Aring/ in order to keep acceptable off-state power consumption at V/sub cc/=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T/sub ox/=26 /spl Aring/) is targeted for V/sub cc/=1.5 V with worst case I/sub off/ <10 pA//spl mu/m and nominal gate delay 24 ps/gate. Another design, named LP1 (T/sub ox/=22 /spl Aring/) is targeted for V/sub cc/=1.2 V with worst case I/sub off/<20 pA//spl mu/m and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 /spl mu/A//spl mu/m nominal drive currents at V/sub cc/ for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 /spl mu/m/sup 2/ cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T/sub ox/=22 /spl Aring/) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125/spl deg/C and V/sub cc/=1.5 V.