Clock Tree Research Articles

Minimal buffer insertion in clock trees with skew and slew rate constraints

In this paper, we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock slew rate (or rise time) constraint and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel nonlinear buffer insertion problem. Next, we derive an algorithm that bounds the capacitance for each buffer stage without sacrificing the generality of the timing models. With this capacitance bound we formulate a second linear buffer insertion problem, which we solve optimally in O(n) time. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0 /spl mu/ models and parameters. Experiments with these test cases show that the buffer insertion algorithms proposed herein can be used effectively for designs with high clock speeds and small skews.

Clock tree distribution

The semiconductor industry is moving toward submicron and deep submicron (0.5 μm and below) technologies. As the chip size keeps decreasing, the chip capacity keeps increasing. New challenges are appearing on high speed ASIC (Application Specified Integrated Circuit) design. Building a balanced clock tree is now essential for the success of any advanced VLSI (Very Large Scale Integration) design. The interconnect wire delay is as important as the logic gate delay.

Clock trees: logical clocks for programs with nested parallelism

A vector clock is a valuable tool for maintaining run time concurrency information in parallel programs. A novel method is presented for modifying vector clocks to make them suitable for programs with nested fork join parallelism (having a variable number of tasks). The resulting kind of clock is called a clock tree, due to its tree structure. The clock tree method compares favorably with other timestamping methods for variable parallelism: task identifier reuse and task recycling. The worst case space requirements of clock trees equals the best case for the latter two methods, and the average size of a clock tree is much smaller than the size of a vector with task recycling. Furthermore, the algorithm for maintaining clock trees does not require a shared data structure and thus avoids the serialization bottleneck that task recycling suffers from.

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations

An integrated top-down design system is presented in this paper for synthesizing clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circuit, and used to determine a non-zero clock skew schedule which reduces the clock period as compared to zero skew-based approaches. Concurrently, the permissible range of clock skew for each local data path is calculated to determine the maximum allowed variation of the scheduled clock skew such that no synchronization failures occur. The choice of clock skew values considers several design objectives, such as minimizing the effects of process parameter variations, imposing a zero clock skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value. The clock skew schedule and the worst case variation of the primary process parameters are used to determine the hierarchical topology of the clock distribution network, defining the number of levels and branches of the clock tree and the delay associated with each branch. The delay of each branch of the clock tree is physically implemented with distributed buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and the characteristics of the clock tree interconnect. A bottom-up approach for calculating the worst case variation of the clock skew due to process parameter variations is integrated with the top-down synthesis system. Thus, the local clock skews and a clock distribution network are obtained which are more tolerant to process parameter variations. This methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide clock frequency of up to 43% as compared with zero clock skew implementations are shown. Furthermore, examples of clock distribution networks that exploit intentional localized clock skew are presented which are tolerant to process parameter variations with worst case clock skew variations of up to 30%.

Circuit Placement, Chip Optimization, and Wire Routing for IBMIC Technology

Recent advances in integrated circuit technology have imposed new requirements on the chip physical design process. At the same time that performance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the chip wiring demand, and the ability to efficiently process these large chips in reasonable time and space requires new capabilities from the physical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successively refined timing-derived constraints. Chip optimization tools are used to physically optimize the clock trees and scan connections, both to improve clock skew and to improve wirability. These tools interchange sinks of equivalent nets, move and create parallel copies of clock buffers, add load circuits to balance clock net loads, and generate balanced clock tree routes. Routing is done using a grid-based, technology-independent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.

Package clock distribution design optimization for high-speed and low-power VLSIs

With continually increased difficulties of the clock distribution in high speed microprocessors and application-specific integrated circuits (ASICs), the package clock distribution shows very promising advantages. The concurrent design of chip and package will provide the optimal design of a clock network by taking the advantages of package layers. The package layers provide 1000 times less wire resistance and 10 times less wire capacitance than those of interconnects on chip. Therefore, it is more beneficial to route the global clock network on package. The implementation issues of the package clock distribution are described in this paper, including the electrostatic discharge (ESD) circuit design for local clock buffers and transmission line noise suppression for package clock trees.

Circuit placement, chip optimization, and wire routing for IBM IC technology

Recent advances in integrated circuit technology have imposed new requirements on the chip physical design process. At the same time that performance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the chip wiring demand, and the ability to efficiently process these large chips in reasonable time and space requires new capabilities from the physical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successively refined timing-derived constraints. Chip optimization tools are used to physically optimize the clock trees and scan connections, both to improve clock skew and to improve wirability. These tools interchange sinks of equivalent nets, move and create parallel copies of clock buffers, add load circuits to balance c lock net loads, and generate balanced clock tree routes. Routing is done using a grid-based, technology-independent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.

Planar clock routing for high performance chip and package co-design

A new concept of chip and package co-design for the clock network is presented in this paper. We propose a two level clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster. The clock signal is then distributed from the main clock driver to each of local buffers by means of a global clock tree, which is a planar tree with equal path lengths. With the flip chip area I/O attachment, the planar global clock tree can be put on a dedicated package layer. The interconnect on the package layer has two to four order smaller resistance than that on the chip layer. The main contribution of this paper is a novel algorithm to construct a planar clock tree with equal path lengths-the length of the path from the clock source to each destination is exactly the same. In addition, the path length from the source to destinations is minimized.

Post-processing of clock trees via wiresizing and buffering for robust design

Achieving near-zero skew for a large clock tree is generally at the expense of adding large amounts of metal interconnect. This added metal can significantly increase the total clock-net capacitance, thereby increasing the power dissipation in proportion. In addition, it is shown that it becomes increasingly difficult to control clock-signal skew due to metal-wiring process variations as the total clock-net capacitance increases. In this paper we demonstrate that buffer insertion can be used to reduce the total capacitance, hence the power, while generating a design which is as robust as one with no intermediate buffering. Moreover, delays are reduced substantially as well. Given an initial feasible route with constraints. On wire widths, wire sizing and buffer insertion are performed concurrently at each iteration of optimal buffer location search. Statistical process variations of the buffers, their loads, and the metal interconnect parameters are considered as part of the robust design process.

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated.

Planar-DME: a single-layer zero-skew clock tree router

This paper presents new single-layer, i.e., planar-embeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The first algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called Elmore-Planar-DME, uses the Linear-Planar-DME connection topology in constructing a low-cost ZST according to the Elmore delay model. While a planar ZST under the linear delay model is easily converted to a planar ZST under the Elmore model by elongating tree edges in bottom-up order, our key idea is to avoid unneeded wire elongation by iterating the DME construction of ZST and the bottom-up modification of the resulting nonplanar routing. Costs of our planar ZST solutions are comparable to those of the best previous nonplanar ZST solutions, and substantially improve over previous planar clock routing methods.

High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

To achieve path delay balance, instead of making faster paths slower by elongating wires used in most zero skew clock routing methods, we make slower paths faster by the wire sizing. The wire sizing technique is frequently used by IC designers to minimize the clock skew caused by the unbalanced RC delays and transmission line noises. However, manual sizing takes a long time and lacks accurate relationship between the timing and wire widths. This paper formulates the optimal clock sizing problem and proposes a sizing optimization algorithm based on Gauss-Marquardt's least square minimization method. The minimum skew is achieved by this method due to its uphill mechanism of searching the global minimum by selecting a proper Lagrange multiplier dynamically at each iteration. The optimization is guided by the delay calculation based on a distributed RLC interconnect model which takes into the account the nonnegligible inductance in high-speed long interconnects (such as on the substrate of a multichip module). The algorithm and delay model can handle a general clock network including loops such as a clock mesh. For testing examples of equal path length clock trees, this algorithm can further achieve 10/spl times/ skew reduction and 14% path delay reduction after the sizing.

A buffer distribution algorithm for high-performance clock net optimization

We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a good tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. Our experiments complement the theoretical results. (2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interconnection delay dominates the clock delay, buffer congestion might exist in a layout. Using many buffers in a small wiring area results in substantial interline crosstalks as well as wirability, when the elongation of the imbalanced subtrees is necessary. Placing buffers evenly (locally or globally) over the plane at the minimum impact on wire length increase helps avoid buffer congestion and results in less crosstalk between clock wires. Thus, an effective technique for buffer distribution is proposed. Experimental results verify the effectiveness of the proposed algorithms. (3) Finally, a postprocessing step constraining on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. The proposed algorithm has an important application in MCM clock net synthesis as well as VLSI clock net synthesis. >

On general zero-skew clock net construction

We propose a simulated annealing based zero-skew clock net construction algorithm that works in any routing spaces, from Manhattan to Euclidean, with the added flexibility of optimizing either the wire length or the propagation delay. We first devise an O(log n) tree grafting perturbation function to construct a zero-skew clock tree under the Elmore delay model. This tree grafting scheme is able to explore the entire solution space asymptotically. A Gauss-Seidel iteration procedure is then applied to optimize the Steiner point positions. Experimental results have shown that our algorithm can achieve substantial delay reduction and encouraging wire length minimization compared to previous works.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Single clock partial scan

Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A dynamic clock synchronization technique for large systems

This paper reports on a circuit technique which can be used to reduce the clock skew in ULSI and WSI systems. It is suitable for large systems which are divided into isochronic modules with locally optimized clock distribution. The inter-module clock distribution uses tunable delay elements to compensate for the differences in the phase delay of the individual modules. The delay elements introduce a phase shift to the clock signals going to each region to align the clock edges at the leaves of the local clock trees. This technique is dynamic in the sense that it guarantees clock synchronization in the presence of process or ambient variations. Whenever the clock skew exceeds a specific limit, the clock synchronization systems is activated to restrain the skew. The advantage of this technique over using phase locked loop circuits is that it saves power consumption and area. In addition, its lock-in time is much shorter. Experiments have shown that using the tunable delay element approach is capable of reducing the skew to less than 100 ps. A stability criterion was developed. The effect of substrate and power supply noise on the synchronization scheme was also investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effective buffer insertion of clock tree for high-speed VLSI circuits : Bo Wu and Naveed A. Sherwani. Microelectronics Journal23, 291 (1992)

Effective buffer insertion of clock tree for high-speed VLSI circuits : Bo Wu and Naveed A. Sherwani. Microelectronics Journal23, 291 (1992)

An exact zero-skew clock routing algorithm

An exact zero-skew clock routing algorithm using the Elmore delay model is presented. The results have been verified with accurate waveform simulation. The authors first review a linear time delay computation method. A recursive bottom-up algorithm is then proposed for interconnecting two zero-skewed subtrees to a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multistaged clock trees, and multi-chip system clock trees. The approach is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, then interconnected with exact zero skew. Extensions to the routing of optimum nonzero-skew clock trees (for cycle stealing) and multiphased clock trees are also discussed. >

Effective buffer insertion of clock tree for high-speed VLSI circuits

Clock delay and skew minimization is an important problem in design and layout of high speed VLSI circuits. Clock delay and skew can be minimized either by a good routing strategy, or by inserting buffers in the clock tree. In this paper we develop an effective buffer insertion algorithm for high speed clock layout to minimize the clock delay and skew. Our approach is based on a new interconnection delay model, in which several practical factors such as crossunders and vias are considered in the delay calculation; furthermore, both minimum-size buffers and cascaded clock buffers are used to minimize the total clock delay. The algorithm runs in O ( n ) time, where n is the number of legal buffer positions in the clock tree, and obtains up to 95% clock delay reduction on practical examples.

Zero skew clock routing with minimum wirelength

The deferred-merge embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength, is presented. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wire length reduction over some previous constructions. The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. A unified BB+DME algorithm, which constructs a clock tree topology using a top-down balanced bipartition (BB) approach and then applies DME to that topology, is also presented. The experimental results indicate that both the topology generation and embedding components of the methodology are necessary for effective clock tree construction. >