Clock Synchronization System Research Articles

Development of prototype system for quantum two-way clock synchronization

In this Letter, we report a prototype system that realizes the complete functionality for quantum two-way time transfer, comparison, and synchronization between two integrated terminals. The synchronization performance was tested over a 50-km spooled fiber link. With the common frequency reference, the time deviation was measured as 0.45 ps at an averaging time of 104 s, which is limited by the system's hardware and determines the minimum achievable synchronization stability. By employing an open-loop fiber-optic microwave frequency transfer in combination with the technique of dynamically identifying and steering the time offset between the terminals, a synchronization stability of 1.26 ps at 104 s was achieved. Further utilizing the grey prediction model to correct the time offset data, the synchronization stability was significantly improved to 0.69 ps at 104 s, showing its potential to enhance the synchronization performance. This report marks the development of a utility quantum two-way clock synchronization system. The ongoing exploration of advanced time-offset adjustment strategies to attain synchronization stability significantly below 1 ps is poised to yield invaluable benefits for future applications.

Design of a high-precision clock distribution and synchronization system

In large-scale nuclear and particle physics experiments, there is a high demand for high precision clock distribution and synchronization. In this paper, the design and testing of a high precision clock distribution and synchronization system for the CSR External Target Experiment (CEE) is presented. To achieve high synchronization precision, a dedicated high-quality clock distribution network is designed, while the timestamp synchronization is achieved over the existing trigger link in CEE with a customized protocol in order to simplify the system structure. Automatic metastability elimination and real-time monitoring of both the timestamps on the front end nodes and the clock electronics status are also implemented. The test results indicate that the period jitter of the clock network is better than 4 ps rms, and all the expected functionalities have been achieved successfully.

The light source of the TRIDENT pathfinder experiment

In September 2021, a site scouting mission known as the TRIDENT pathfinder experiment (TRIDENT EXplorer, T-REX for short) was conducted in the South China Sea with the goal of envisaging a next-generation multi-cubic-kilometer neutrino telescope. One of the main tasks is to measure the in-situ optical properties of seawater at depths between 2800 m and 3500 m, where the neutrino telescope will be instrumented. To achieve this, we have developed a light emitter module equipped with a clock synchronization system to serve as the light source, which could be operated in pulsing and steady modes. Two light receiver modules housing both photomultiplier tubes (PMTs) and cameras are employed to detect the photons emitted by the light source. This paper presents the instrumentation of the light source in T-REX, including its design, calibration, and performance.

Development Board Implementation and Chip Design of IEEE 1588 Clock Synchronization System Applied to Computer Networking

With the vigorous development of industrial automation and the Internet of things, the transmission of data is more dependent on immediacy, so network devices have higher and higher requirements for time synchronization accuracy. The clock source of common network devices is provided by the transistor oscillator in the server, but the oscillator will change with factors such as aging and temperature, and it cannot be guaranteed that the oscillator in the server will work at the same frequency. Time synchronization can be achieved by technologies such as IRIG-B, NTP, or IEEE 1588 (PTP), but the hardware cost of building IRIG-B is high, and NTP has the lowest cost, but it can only provide time accuracy from milliseconds to microseconds. PTP can provide sub-microsecond or even nanosecond time precision. It is a system of time synchronization mechanisms through Ethernet transmission. In this article, we first propose a time synchronization system using the development board and PDP protocol. On the Xilinx Zynq-7000 SOC platform of Petalinux, we implement the hardware solution of Linux PTP. The hardware time stamp is 20 ns. To improve the accuracy, the congenital frequency error between the oscillators must be considered. Therefore, a PTP auxiliary time stamp with dynamic frequency compensation is proposed and designed into a chip. Experimental results show that at 45 nm (TN40G) it can operate at 370 MHz and achieve 2.7 ns resolution, which can be applied to more demands.

Stable frequency transfer for clock synchronization for telecom networks

A stable and reliable clock synchronization system that transfers reference clocks to nodes is essential for telecom networks. Mainly, the clock synchronization of telecom networks is carried out through satellite links. However, for the evolving ubiquitous wireless communications, especially in some harsh environments, such as underground and trenches, the satellite-based clock synchronization scheme bears inevitable obstacles, which may cause strategic risks for the telecom networks, since no control and manipulation can be imposed on the satellite systems. Therefore, to ensure the robust operation of telecom networks with performance guarantees, some auxiliary means are desirable to assist clock synchronization that is solely based on satellite links. In this article, we report a phase-stabilized frequency signal transmission on branching optical fiber for clock synchronization for telecom networks. Particularly, the phase fluctuation due to optical carriers separation link and fiber link is compensated by a feedback network, which employs a high-precision voltage-controlled oscillator in the phase-locked loop to drive the acousto-optic frequency shifter for fast phase correction. Furtherly, the factors that cause performance limitations of the frequency distribution system are analyzed. Eventually, the experiment results obtained show that a stabilized fiber-optic frequency transfer scheme can be used as a reliable method for clock synchronization with high accuracy.

Robust Time Synchronization for Industrial Internet of Things by H ∞ Output Feedback Control

Precise timing over timestamped packet-exchange communication is an enabling technology in the mission-critical industrial Internet of Things (IIoT), particularly when satellite-based timing is unavailable. The main challenge is to ensure timing accuracy when the clock synchronization system is subject to disturbances caused by the drifting frequency, time-varying delay, jitter, and timestamping uncertainty. In this work, a robust packet-coupled oscillators (R-PkCOs) protocol is proposed to reduce the effects of perturbations manifested in the drifting clock, timestamping uncertainty, and delays. First, in the spanning-tree clock topology, time synchronization between an arbitrary pair of clocks is modeled as a state-space model, where clock states are coupled with each other by one-way timestamped packet exchange (referred to as packet coupling), and the impacts of both drifting frequency and delays are modeled as disturbances. A static output controller is adopted to adjust the drifting clock. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$H_{\infty }$ </tex-math></inline-formula> robust control design solution is proposed to guarantee that the ratio between the modulus of synchronization precision and the magnitude of the disturbances are always less than a given value. Therefore, the proposed time synchronization protocol is robust against the disturbances, which means that the impacts of drifting frequency and delays on the synchronization accuracy are limited. The one-hour experimental results demonstrate that the proposed R-PkCO’s protocol can realize time synchronization with the precision of 6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> in a 21-node IEEE 802.15.4 network. This work has widespread impacts in the process automation of automotive, mining, oil, and gas industries.

Design considerations for hardware implementation of nanoseconds time synchronization low-cost system based on precise time protocol

Precise time synchronization is the key for coordinating every node of the distributed system to complete tasks. The widespread use of Field Programmable Gate Array (FPGA) in distributed nodes has a positive effect on improving time synchronization accuracy. Although the use of FPGA could significantly improve time synchronization accuracy, there is not a universal design guideline. This work has analyzed and summarized three factors that should be considered when building a low-cost clock synchronization system using FPGA: where the timestamp should be generated, the calculation and correction of time offset, and how to handle Precise Time Protocol (PTP) messages. Based on these design considerations, the time synchronization system intellectual property (IP) core was constructed. The synchronization accuracy experiments have been performed on Zynq system-on-chip (SoC) evaluation boards of different architectures. The experimental results demonstrated that the time synchronization system constructed in this article could achieve nanoseconds accuracy.

Implementation of a Circuit for Precise Time Stamping of Synchronous Message

Highly required by distributed network operation, the clock synchronization technology is very important. The transmit time of synchronization packets should be stamped precisely in a clock synchronization system. Time stamping in the physical layer is necessary to obtain the time precisely. This paper introduces a general precision time stamping circuit based on 10Mb/s and 100Mb/s transmission. The circuit is designed and manufactured in 0.18μm CMOS technology supporting Precise Timing Protocol based on IEEE 1588. The circuit is verified by an experimental system. The test results show that the general precision time stamping circuit can mark the stamps for UDP/IPv4 Ethernet format in the physical layer. The circuit has an ability to mark a time stamp in less than 60μs.

Implementation of a twin-beam state-based clock synchronization system with dispersion-free HOM feedback.

In the field of clock synchronization, the application of frequency-entangled source is a promising direction to improve accuracy and security. In this paper, we analyze the performance of the twin-beam state and the difference-beam state using a practical second-order interference-based scheme. The advantages of the twin-beam state are pointed out especially for the dispersion-free property of HOM interference in a long-distance clock transfer. With the introduction of dispersion-compensated material, our experimental system based on a twin-beam state achieves a clock accuracy at 4 ps with a time offset precision of 1.8 ps over 10 s acquisition time while the time deviation is 0.15 ps over an averaging time of 5500 s in a 22 km-long transmission. These properties exhibit a leading position compared with the current clock synchronization system using the same theoretical scheme and also competitive among the implementations using other second-order interference-based schemes.

Особенности построения систем тактовой сетевой синхронизации для распределенных сетей связи

Modern high-speed telecommunication networks with time division multiplexing (TDM) based on nx64kBit/s channel switching cannot function without a high-quality network synchronization system, which is designed to ensure the reliability and stability of the formation, switching and processing of information in digital channels. The clock synchronization system is based on the transmission of the reference frequency from the primary clock to all digital equipment of the telecommunication network through the high-speed streams of transmission systems. However, in the case of distributed communication networks, the integrity of the clock synchronization system is violated, and there is a need to develop special technical solutions to ensure the provision of frequencies for all remote network elements. This article is devoted to an overview of such solutions.

Research and Implementation of Clock Synchronization Technology Based on PTP

With the rapid development of power system, the requirement of network clock synchronization accuracy is becoming higher and higher, in many cases, it needs to reach microsecond level. In order to meet the increasing demand, based on the analysis of the basic principle of PTP clock synchronization protocol, a physical layer clock synchronization system based on STM32 MCU and DP83640 chip is proposed. The system synchronization time error is less than 1 microsecond by using the timeacc-007 time precision measuring instrument. The scheme meets the requirements of accurate clock synchronization for all distributed nodes in the power system.

Scalable clock synchronization analysis: A symmetric noncooperative output feedback tubes-MPC approach

In the cyber-physical environment, the clock synchronization algorithm is required to have better expansion for network scale. In this paper, a new measurement model of observability under the equivalent transformation of minimum mean square error ( MMSE ) is constructed based on basic measurement unit ( BMU ) , which can realize the scaled expansion of MMSE measurement. Based on the state updating equation of absolute clock and the decoupled measurement model of MMSE-like equivalence, which is proposed to calculate the positive definite invariant set by using the theoretical-practical Luenberger observer as the synthetical observer, the local noncooperative optimal control problem is built, and the clock synchronization system driven by the ideal state of local clock can reach the exponential convergence for synchronization performance. Different from the problem of general linear system regulators, the state estimation error and state control error are analyzed in the established affine system based on the set-theory-in-control to achieve the quantification of state deviation caused by noise interference. Based on the BMU for isomorphic state map, the synchronization performance of clock states between multiple sets of representative nodes is evaluated, and the scale of evaluated system can be still expanded. After the synchronization is completed, the state of perturbation system remains in the maximum range of measurement accuracy, and the state of nominal system can be stabilized at the ideal state for local clock and realizes the exponential convergence of the clock synchronization system.

Resilience Bounds of Network Clock Synchronization with Fault Correction

Naturally occurring disturbances and malicious attacks can lead to faults in synchronizing the clocks of two network nodes. In this article, we investigate the fundamental resilience bounds of network clock synchronization for a system of N nodes against the peer-to-peer synchronization faults. Our analysis is based on practical synchronization algorithms with time complexity down to O ( N 3 ) that attempt to correct the faults by checking the consistency among the following three types of data: (1) the estimated faults, (2) the estimated clock offsets among the nodes, and (3) the measured clock offsets from the potentially faulty peer-to-peer synchronization sessions. Our analysis gives the following three major results. First, the maximum number of faults that can be corrected by the algorithms has a tight bound of ⌊ N /2 ⌋ − 1 when every node pair performs a synchronization session. Second, by converting the fault resilience problem to a graph-theoretic edge connectivity problem and applying Menger’s theorem, we develop an algorithm to compute the tight bound when not every node pair performs a synchronization session. Third, the number of synchronization sessions to achieve the capability of correcting any K faults has a lower bound of ⌈ N (2 K +1) / 2 ⌉ ; we also develop an algorithm to schedule the synchronization sessions to approach the lower bound. The above results provide basic understanding and useful guidelines to the design of resilient clock synchronization systems. For instance, our results suggest that, the four-node network achieves the highest degree of resilience that is defined as the ratio of the maximum number of correctable faults to the number of synchronization sessions. Therefore, by organizing a large-scale clock synchronization system into a hierarchy of multiple tiers with each consisting of four-node synchronization groups, we can achieve satisfactory and understood resilience against faults with reduced synchronization sessions.

Precise clock synchronization for radio frequency positioning system based on White Rabbit PTP

Use case of the White Rabbit Precision Time Protocol (PTP) sub-nanosecond clock synchronization system in complex with Time-to-Digital Converter (TDC) is examined for precise time of RF signal arrival capture. Implemented WR PTP core port on target hardware platform is explained. TDC placement method for Intel Quartus Prime tool is also shown.

BLAS: Broadcast Relative Localization and Clock Synchronization for Dynamic Dense Multiagent Systems

The spatiotemporal information plays crucial roles in a multi-agent system (MAS). However, for a highly dynamic and dense MAS in unknown environments, estimating its spatiotemporal states is a difficult problem. In this paper, we present BLAS: a wireless broadcast relative localization and clock synchronization system to address these challenges. Our BLAS system exploits a broadcast architecture, under which a MAS is categorized into parent agents that broadcast wireless packets and child agents that are passive receivers, to reduce the number of required packets among agents for relative localization and clock synchronization. We first propose an asynchronous broadcasting and passively receiving (ABPR) protocol. The protocol schedules the broadcast of parent agents using a distributed time division multiple access (D-TDMA) scheme and delivers inter-agent information used for joint relative localization and clock synchronization. We then present distributed state estimation approaches in parent and child agents that utilize the broadcast inter-agent information for joint estimation of spatiotemporal states. The simulations and real-world experiments based on ultra-wideband (UWB) illustrate that our proposed BLAS cannot only enable accurate, high-frequency and real-time estimation of relative position and clock parameters but also support theoretically an unlimited number of agents.

Research Based on IEEE1588 Frequency Compensation Algorithm

The paper first studies the IEEE1588 network clock synchronization system. Aiming at the instability of the system clock crystal oscillator, a frequency compensation algorithm is proposed, which can adjust the master-slave clock frequency and ensure the master-slave clock synchronization. The simulation analysis shows that when the master-slave clock generates the deviation value, the master-slave clock is consistent with the execution of the frequency compensation algorithm, which verifies the feasibility and effectiveness of the algorithm.

Influence of synchronization errors оn the noise immunity of coherent reception of M-PSK signals

Signals with multiple phase-shift keying (M-PSK) have long been successfully used for highspeed information transfer in many applications – a number of adopted protocols of IEEE 802.11 wireless networks, digital satellite television DVB-S, DVB-S2/S2X systems, cellular networks CDMA and others. The most important characteristic of such systems is their noise immunity, which depends not only on the propagation conditions of radio waves in the communication channel, but also on the quality of operation of the component nodes of the information transmission systems themselves. The paper investigates the influence of the inaccuracy of estimating the frequency and phase of the carrier and the inaccuracy of the clock synchronization system on the noise immunity of coherent reception of M-PSK signals. Analytical expressions were obtained by statistical radio engineering methods. The expressions allow calculating the dependence of the probability of a bit error on the signal-to-noise ratio for various errors of the receiver auxiliary systems. In this case, the magnitudes of the errors were assumed to be either constant (static error) or dynamically changing (dynamic error). The dynamic errors were modeled using the Monte Carlo method, and the dynamic errors themselves were assumed to be Gaussian random variables. It is shown that the inaccuracy of estimating these parameters strongly influences the noise immunity of the coherent reception of the M-PSK signal, and this effect increases with increasing signal positionality. Estimates of the maximum permissible errors of the analyzed systems are given. When M-PSK signals are received, a tolerable value of the frequency of the reference oscillations can be considered as a ∆ωTs value of about 0.05. The allowable inaccuracy of the carrier phase estimation depends on the positioning of the signal and varies from π/36–π/72 for 2PSK to π/180 for 32PSK. The allowable time offset of the clock moments can be considered the value of 3–5% of the clock interval duration.

Signal processing with frequency and phase shift keying modulation in telecommunications

In this paper represents research improving effectiveness of signal processing in telecommunication devices especially for its part, which relates to providing its noise resistance in conditions of noise and interference. This objective has been achieved through development of methods and means for optimization of filtering devices and semigraphical interpretation of clock synchronization systems in telecommunications with frequency shift keying on the base of stochastic models what determines relevance of the subject. Separately, in an article considered the urgent task is using of modified synchronization methods based on the interference influence of adjacent symbols on the phase criterion tract, in particular the use of the modified synchronization scheme, in order to get a formalized outlook representation of the synchronization schemas based on the polyphase structures with using a bank of filters, that allows to improve the characteristics of digital telecommunication channels. This work is devoted to the examination and modeling of these ways. The proposed ideas and results for the construction of synchronization systems can be used in modern means of telecommunication.

Optimization of Clock Synchronization System Architecture in Nuclear Power Plant

Clock Synchronization System (CSS) can generate standard time, time and frequency signals, and provide various high-precision time reference signals for systems and equipment requiring standard time scale in nuclear power plants. With the rapid development of power system, the requirement of time synchronization is becoming more and more urgent, which requires accurate, safe and reliable clock sources. The structure of nuclear power plant clock synchronization system is constantly optimized to meet the requirements of time synchronization of various systems and equipment, to ensure the time consistency of real-time data acquisition, to improve reliability and to adapt to the interconnection of large power grids in China. At the same time, the interconnection between time synchronization system and time-service equipment or system, and the interconnection of first-level time synchronization system network and operation mode of time synchronization devices from different manufacturers are standard

Requirements for Secure Clock Synchronization

This paper establishes a fundamental theory of secure clock synchronization. Accurate clock synchronization is the backbone of systems managing power distribution, financial transactions, telecommunication operations, database services, etc. Some clock synchronization (time transfer) systems, such as the Global Navigation Satellite Systems (GNSS), are based on one-way communication from a master to a slave clock. Others, such as the Network Transport Protocol (NTP), and the IEEE 1588 Precision Time Protocol (PTP), involve two-way communication between the master and slave. This paper shows that all one-way time transfer protocols are vulnerable to replay attacks that can potentially compromise timing information. A set of conditions for secure two-way clock synchronization is proposed and proved to be necessary and sufficient. It is shown that IEEE 1588 PTP, although a two-way synchronization protocol, is not compliant with these conditions, and is therefore insecure. Requirements for secure IEEE 1588 PTP are proposed, and a second example protocol is offered to illustrate the range of compliant systems.