Clock Frequency Research Articles

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence.

In recent years, edge intelligence (EI) has emerged, combining edge computing with AI, and specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power consumption, size, and cost, with the primary challenge being the trade-off between computational power and power consumption. This has rendered traditional computing platforms unsustainable, making heterogeneous parallel computing platforms a crucial pathway for implementing EI. In our research, we leveraged the Xilinx Zynq 7000 heterogeneous computing platform, employed high-level synthesis (HLS) for design, and implemented two different accelerators for LeNet-5 using loop unrolling and pipelining optimization techniques. The experimental results show that when running at a clock speed of 100 MHz, the PIPELINE accelerator, compared to the UNROLL accelerator, experiences an 8.09% increase in power consumption but speeds up by 14.972 times, making the PIPELINE accelerator superior in performance. Compared to the CPU, the PIPELINE accelerator reduces power consumption by 91.37% and speeds up by 70.387 times, while compared to the GPU, it reduces power consumption by 93.35%. This study provides two different optimization schemes for edge intelligence applications through design and experimentation and demonstrates the impact of different quantization methods on FPGA resource consumption. These experimental results can provide a reference for practical applications, thereby providing a reference hardware acceleration scheme for edge intelligence applications.

Upper bounds for the clock speeds of fault-tolerant distributed quantum computation using satellites to supply entangled photon pairs

Upper bounds for the clock speeds of fault-tolerant distributed quantum computation using satellites to supply entangled photon pairs

Effects of Electrons on Nuclear Clock Transition Frequency in ^{229}Th Ions.

We perform calculations of the energy shift of the nuclear clock transition frequency ^{229}Th as a function of the number of electrons in Th ion. We demonstrate that the dependence of the nuclear frequency on electron configuration is significant, for example, removing one electron from the atom leads to relative shift of the nuclear frequency ∼10^{-7}, which is 12 orders of magnitude larger than the expected relative uncertainty of the nuclear clock transition frequency (∼10^{-19}). This leads to the difference of the nuclear clock frequencies in Th IV, Th III, Th II, and Th I. The relative change of the nuclear frequency between neutral Th and its bare nucleus is 1%. We also calculate the field shift constants for isotopic and isomeric shifts of atomic electron transitions in Th ions.

Custom ASIC Design for SHA-256 Using Open-Source Tools

The growth of digital communications has driven the development of numerous cryptographic methods for secure data transfer and storage. The SHA-256 algorithm is a cryptographic hash function widely used for validating data authenticity, identity, and integrity. The inherent SHA-256 computational overhead has motivated the search for more efficient hardware solutions, such as application-specific integrated circuits (ASICs). This work presents a custom ASIC hardware accelerator for the SHA-256 algorithm entirely created using open-source electronic design automation tools. The integrated circuit was synthesized using SkyWater SKY130 130 nm process technology through the OpenLANE automated workflow. The proposed final design is compatible with 32-bit microcontrollers, has a total area of 104,585 µm2, and operates at a maximum clock frequency of 97.9 MHz. Several optimization configurations were tested and analyzed during the synthesis phase to enhance the performance of the final design.

Scalable Data Concentrator with Baseline Interconnection Network for Triggerless Data Acquisition Systems

Triggerless data acquisition systems (DAQs) require that the data stream is transmitted from multiple links and into the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO) for high-speed data routing. A thorough analysis of the network’s operation enabled increased scalability compared to the previously published concentrator based on an 8 × 8 network. The solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were performed for four and five layers (16 and 32 inputs). The FPGA implementation and tests in the actual hardware were successfully performed for 16 inputs. The pipeline registers may be added in each layer independently, shortening the critical path and increasing the maximum acceptable clock frequency.

Ternary Instantaneous Noise-Based Logic with Exponential Hilbert Space

A tree-valued instantaneous noise-based logic with exponential Hilbert space is proposed. The third value is an uncertain bit value, which can be useful in artificial intelligence applications. The signal carrying the ternary universe has a significant advantage over the signal of the standard binary universe: its amplitude is never zero during any clock period. All known binary logic gates for exponential Hilbert space work for the binary sub-space in the ternary logic in the same way as they do in binary logic. This is useful when zeros cause problems in the exponential Hilbert space version of binary logic. Ternary logic is advantageous in various applications, including AI and natural language processing.

Improved DWT and IDWT architectures for image compression

In the recent era, a rapid development in the field of image processing has been observed. One of the important applications in image processing is compression. Several wavelet transform based image compression techniques have already been introduced. In this paper, Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) based improved image compression and decompression techniques have been proposed by incorporating a scaling factor. The DWT and IDWT algorithms are implemented using folded architecture. To reduce the usages of hardware resources, a multiplier is recursively used. Image compression and decompression schemes based on proposed DWT and IDWT architectures are tested using four different image databases. The proposed technique provides better results in terms of bits per pixel, compression ratio, mean square error, peak-signal-to-noise ratio, normalized correlation coefficient and structural similarity index. FPGA based synthesis has been performed using Xilinx Vivado Synthesis tool in terms of slice LUTs, slice registers, clock frequency, delay and power. The synthesis results show that proposed DWT and IDWT architectures are amenable for image compression and decompression applications.

Clock synchronizing radio access networks to picosecond precision using optical clock distribution and clock phase caching

Performing positioning of future mobile devices using trilateration through radio access networks would provide a robust alternative to currently used global navigation satellite systems. However, the positioning accuracy is strongly dependent on the time synchronization accuracy of the antennas used as location reference points. Consequently, achieving sub-30 cm positioning accuracies requires the synchronization of radio access network antennas to sub-nanosecond accuracy. Here we show a clock phase synchronization and optical clock signal distribution approach to clock synchronization in radio access networks that achieves 0.98-ps root-mean-square precision clock synchronization, in a real-time field-trial demonstration on 37.6-km dark fiber, with optical clock frequency synchronization and clock phase caching operating using 25.6-Gb/s commercial transceivers. We quantify the clock synchronization performance of our approach using standard metrics, including time deviation (TDEV) and mean time interval error (MTIE). Furthermore, we estimate the impact of varying the phase update rate used in clock phase caching on the clock synchronization performance of our approach. Through our two combined approaches, we explore a route towards achieving sub-nanosecond clock synchronization in radio access networks.

IMPLEMENTATION OF FUNCTIONAL BLOCK RADIO UNIT BASED ON SYSTEM-ON-CHIP

This article discusses the implementation of the Radio Unit functional block based on the System-on-Chip. The primary focus was on integrating Radio Unit blocks such as modulation and Fast Fourier Transform on Field-Programmable Gate Array. Technical aspects of design, module testing, and Radio Unit block performance optimization are thoroughly examined. The results demonstrate that when separating the functionality of the 7.3 technology Fifth Generation (5G) radio block, the modulation module uses the minimum Field-Programmable Gate Array resources compared to other blocks. The Fast Fourier Transform block can meet delay requirements at the maximum Field-Programmable Gate Array size and clock frequency of 250 MHz. This article serves as a resource for engineers and researchers interested in optimizing the development and integration process of high-performance functional blocks in modern radio systems.

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route

Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure. This work focuses on timing prediction after clock tree synthesis and placement legalization, which is the earliest opportunity to time and optimize a “complete” netlist. The article first documents that having “oracle knowledge” of the final post-DR parasitics enables post-global routing (GR) optimization to produce improved final timing outcomes. To bridge the gap between GR-based parasitic and timing estimation and post-DR results during post-GR optimization , machine learning (ML)-based models are proposed, including the use of features for macro blockages for accurate predictions for designs with macros. Based on a set of experimental evaluations, it is demonstrated that these models show higher accuracy than GR-based timing estimation. When used during post-GR optimization, the ML-based models show demonstrable improvements in post-DR circuit performance. The methodology is applied to two different tool flows—OpenROAD and a commercial tool flow—and results on an open-source 45nm bulk and a commercial 12nm FinFET enablement show improvements in post-DR timing slack metrics without increasing congestion. The models are demonstrated to be generalizable to designs generated under different clock period constraints and are robust to training data with small levels of noise.

CFD microscale modelling of flow behavior in different parts of a rotating packed bed

Process intensification (PI) is playing a key role in alleviating the challenge of reducing carbon footprint of many chemical processes and bringing down their development costs. Over the years, many PI technologies have been investigated with rotating packed bed (RPB) technology receiving much of the attention for its potential of significant intensification in terms of capital expenditure, operating costs, and hardware size. In this study, microscale CFD simulations of a rotating packed bed were conducted, and the results were validated with experimental data. The results show the strong relation between the reverse flow at the packing outer periphery and the gas maldistribution factor. The latter is mainly caused by the accelerating flow in the outer cavity. Inside the wire mesh packing, the gas flow is found to be almost fully uniform for nearly half of the total packing depth. Also, turbulent kinetic energy (TKE) levels at the packing outer edge are strongly linked to the slip tangential velocity component, while at its inner edge, they depend mainly on the radial packing velocity. The so-called gas end effect zone is detected by observing the TKE profiles near the packing outer edge. The latter accounts for less than 10% of the total packing depth. The validity of the widely used porous media model in RPBs’ packing for both radial and tangential directions is confirmed by the obtained results, but this excludes the packing inner and outer edges. In the inner cavity region, gas exhibits two distinctive behaviors and transits from free vortex flow to swirling flow as the flow becomes close to the vortex core. As a result of this transition, the increase in shear stress accelerates the decrease in the gas tangential velocity in the vortex core and help speed up the favorable pressure gradient and flow establishment beyond the vortex core.

MODELING THE INFLUENCE OF COMPONENTS LEAKAGE CURRENTS ON THE ACCURACY OF THE RECURRENT LADCS

This work is dedicated to the investigation of errors in the recurrent logarithmic analog-to-digital converters (LADC). A generalized structural diagram of the recurrent LADC with a variable logarithmic base is provided. The implementation features and operating principles are explained. Models of the recurrent LADCs that account for the influence of component leakage currents in the converter circuits have been developed. The models consider changes in the structure of the recurrent LADCs during the conversion process. To improve the speed of LADCs, analog switches with an operational amplifier have been used, reducing the switch resistance in the ON state. This increased the clock frequency to 500 kHz, but also increased leakage currents. For the developed 8-bit the recurrent LADCs operating with 10 – and 12-bit output code precision, errors from leakage currents do not exceed (0.45 and 1.37)× 10-3 % for conversion times not exceeding (28 and 78) μs (14 and 39 conversion cycles). Increasing the resolution of the LADCs and their output code results in an increase in these mentioned errors, but they remain significantly smaller than the corresponding quantization errors. However, with each 2 bits of increased precision, the conversion time of the recurrent LADCs increases by 1,5 times. Therefore, increasing precision by more than 2-4 bits is not practical. Key words: recurrent logarithmic ADCs, modeling, leakade current, speed, accuracy

Spatio-temporal coherence of circadian clocks and temporal control of differentiation in Anabaena filaments.

Circadian clock arrays in multicellular filaments of the heterocyst-forming cyanobacterium Anabaena sp. strain PCC 7120 display remarkable spatio-temporal coherence under nitrogen-replete conditions. To shed light on the interplay between circadian clocks and the formation of developmental patterns, we followed the expression of a clock-controlled gene under nitrogen deprivation, at the level of individual cells. Our experiments showed that differentiation into heterocysts took place preferentially within a limited interval of the circadian clock cycle, that gene expression in different vegetative intervals along a developed filament was discoordinated, and that the circadian clock was active in individual heterocysts. Furthermore, Anabaena mutants lacking the kaiABC genes encoding the circadian clock core components produced heterocysts but failed in diazotrophy. Therefore, genes related to some aspect of nitrogen fixation, rather than early or mid-heterocyst differentiation genes, are likely affected by the absence of the clock. A bioinformatics analysis supports the notion that RpaA may play a role as master regulator of clock outputs in Anabaena, the temporal control of differentiation by the circadian clock and the involvement of the clock in proper diazotrophic growth. Together, these results suggest that under nitrogen-deficient conditions, the clock coherent unit in Anabaena is reduced from a full filament under nitrogen-rich conditions to the vegetative cell interval between heterocysts.IMPORTANCECircadian clocks, from unicellular organisms to animals, temporally align biological processes to day and night cycles. We study the dynamics of a circadian clock-controlled gene at the individual cell level in the multicellular filamentous cyanobacterium Anabaena, under nitrogen-stress conditions. Under these conditions, some cells along filaments differentiate to carry out atmospheric nitrogen fixation and lose their capability for oxygenic photosynthesis. We found that clock synchronization is limited to organismic units of contiguous photosynthetic cells, contrary to nitrogen-replete conditions in which clocks are synchronized over a whole filament. We provided evidence that the circadian clock regulates the process of differentiation, allowing it to occur preferentially within a limited time window during the circadian clock period. Lastly, we present evidence that the signal from the core clock to clock-regulated genes is conveyed in Anabaena as in unicellular cyanobacteria.

WRA-MF: A Bit-Level Convolutional-Weight-Decomposition Approach to Improve Parallel Computing Efficiency for Winograd-Based CNN Acceleration

FPGA-based convolutional neural network (CNN) accelerators have been extensively studied recently. To exploit the parallelism of multiplier–accumulator computation in convolution, most FPGA-based CNN accelerators heavily depend on the number of on-chip DSP blocks in the FPGA. Consequently, the performance of the accelerators is restricted by the limitation of the DSPs, leading to an imbalance in the utilization of other FPGA resources. This work proposes a multiplication-free convolutional acceleration scheme (named WRA-MF) to relax the pressure on the required DSP resources. Firstly, the proposed WRA-MF employs the Winograd algorithm to reduce the computational density, and it then performs bit-level convolutional weight decomposition to eliminate the multiplication operations. Furthermore, by extracting common factors, the complexity of the addition operations is reduced. Experimental results on the Xilinx XCVU9P platform show that the WRA-MF can achieve 7559 GOP/s throughput at a 509 MHz clock frequency for VGG16. Compared with state-of-the-art works, the WRA-MF achieves up to a 3.47×–27.55× area efficiency improvement. The results indicate that the proposed architecture achieves a high area efficiency while ameliorating the imbalance in the resource utilization.

Introduction, Dispersal, and Predominance of SARS-CoV-2 Delta Variant in Rio Grande do Sul, Brazil: A Retrospective Analysis.

Mutations in the SARS-CoV-2 genome can alter the virus' fitness, leading to the emergence of variants of concern (VOC). In Brazil, the Gamma variant dominated the pandemic in the first half of 2021, and from June onwards, the first cases of Delta infection were documented. Here, we investigate the introduction and dispersal of the Delta variant in the RS state by sequencing 1077 SARS-CoV-2-positive samples from June to October 2021. Of these samples, 34.7% were identified as Gamma and 65.3% as Delta. Notably, 99.2% of Delta sequences were clustered within the 21J lineage, forming a significant Brazilian clade. The estimated clock rate was 5.97 × 10-4 substitutions per site per year. The Delta variant was first reported on 17 June in the Vinhedos Basalto microregion and rapidly spread, accounting for over 70% of cases within nine weeks. Despite this, the number of cases and deaths remained stable, possibly due to vaccination, prior infections, and the continued mandatory mask use. In conclusion, our study provides insights into the Delta variant circulating in the RS state, highlighting the importance of genomic surveillance for monitoring viral evolution, even when the impact of new variants may be less severe in a given region.

A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoMJ) of −238.0 dB.

Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s

Digitizing side-channel signals at high sampling rates produces huge amounts of data, while side-channel analysis techniques only need those specific trace segments containing Cryptographic Operations (COs). For detecting these segments, waveform-matching techniques have been established comparing the signal with a template of the CO’s characteristic pattern. Real-time waveform matching requires highly parallel implementations as achieved by hardware design but also reconfigurability as provided by FPGAs to adapt the matching hardware to a specific CO pattern. However, currently proposed designs process the samples from analog-to-digital converters sequentially and can only process low sampling rates due to the limited clock speed of FPGAs. In this paper, we present a parallel waveform-matching architecture capable of performing high-speed waveform matching on a high-end FPGA-based digitizer. We also present a workflow for calibrating the waveform-matching system to the specific pattern of the CO in the presence of hardware restrictions provided by the FPGA hardware. Our implementation enables waveform matching at 10 GS/s, offering a speedup of 50x compared to the fastest state-of-the-art implementation known to us. We demonstrate how to apply the technique for attacking the widespread XTS-AES algorithm using waveform matching to recover the encrypted tweak even in the presence of so-called systemic noise.

Circuit Techniques for Immunity to Process, Voltage, and Temperature Variations in the Attachable Fractional Divider

In the automotive industry, system-on-chips are crucial for managing weak radio waves from space, known as satellite signals. Integer-N phase-locked loops have played a vital role in the operation of system-on-chips in recent history. Their clock frequencies are carefully designed to prevent electromagnetic interference. However, as global navigation satellite system becomes more prevalent, integer-N phase-locked loops face new challenges in generating clocks within the shrinking frequency bands due to large frequency steps determined using a reference clock. To address it, replacing integer-N phase-locked loops with fractional-N phase-locked loops is required. This topic has not been discussed extensively, but it is a practical issue that requires consideration due to its potential impact on development costs. This is why we developed an attachable fractional divider. Our developed divider can efficiently transform integer-N phase-locked loops into fractional-N phase-locked loops, achieving low jitter degradation of 0.35 psrms and a low fractional spur of −69.3 dBc. Thanks to its attachable design, it expedites time-to-market. Regarding mass production, ensuring immunity to process, voltage, and temperature variations is a significant concern. We introduce the circuit techniques employed in the developed fractional divider for immunity to process, voltage, and temperature variations. Subsequently, we provide a comprehensive set of measurement results. The frequency differences over process variations in fractional-N mode is 6.14 ppm. Power supply and temperature dependances are extremely small in spread-spectrum clocking mode. This article illustrates that the developed fractional divider enhances both time-to-market and product reliance.

Universal and Reversible Gate Design in Quantum-dot Cellular Automata Nanotechnology

Background: Growing progress in the field of nanoelectronics necessitates ever more advanced nanotechnology due to the continued scaling of conventional devices. For the purpose of fabricating current integrated circuits (ICs), Quantum-dot cellular automata (QCA) nanotechnology is the most suitable substitute for complementary metal oxide semiconductor (CMOS) technology. The problem of short-channel secondary effects at the ultra-nanoscale level confronts CMOS technology Aims: QCA nanotechnology overcomes the issues of conventional logic circuit design methods due to its numerous advantages. This research work aims to design an energy-efficient, reliable, universal, 3×3, and reversible logic gate for the implementation of various logical and Boolean functions in QCA nanotechnology. Objective: It is desirable for portable systems to have a small size, extremely low power consumption, and a clock rate in the terahertz. As a result, QCA nanotechnology is an incredible advancement for digital system applications and the design of future systems. Methods: This research article proposes a novel, ultra-efficient, multi-operative, 3×3 universal reversible gate implemented in QCA nanotechnology using precise QCA cell interaction. The proposed gate is used for the implementation of all the basic logic gates to validate its universality. The implementation of all thirteen standard Boolean functions establishes the proposed gate's multi-operational nature. The energy dissipation analysis of the design has been presented for the varying setups. Results: The proposed gate is area-efficient because it uses minimum QCA cells. Various logical and Boolean functions are effectively implemented using the proposed gate. The result analysis establishes the minimum energy dissipation of the proposed design and endorses it as an ultra-efficient design. Conclusion: The QCA cell interaction method demonstrates the best way to design a universal, reversible, and multi-operative gate.

Switching Capacitor Filter with Multiple Functions, Adjustable Bandwidth in the Range of 5 Hz–10 kHz

This article proposes a second-order switch-capacitor filter that integrates low-pass, high-pass, band-pass, band-stop, and all-pass, and achieves flexible bandwidth adjustment of the filter through clock rate and capacitance ratio. The final filter design consists of two completely independent second-order switch-capacitor filter channels, and a 4-order Butterworth low-pass filter is designed through two-stage cascades. The two completely independent second-order switch-capacitor filters are integrated on a single chip and manufactured using the Huahong BCD350GE high-voltage 24 V process. The measurement results indicate that the proposed switch-capacitor filter achieves various functional filtering characteristics and achieves a bandwidth of 5 Hz to 10 kHz. The chip area is 5.1 × 3.1 mm2, powered by a dual power supply of ± 5 V, and the power consumption is 80 mW.