Clock Gating Technique Research Articles

Easy and difficult exact covering problems arising in VLSI power reduction by clock gating

Several graph matching and exact covering problems arising in VLSI low-power design optimization by clock gating are presented. To maximize the power savings, clock gating requires optimal grouping of Flip-Flops (FFs), which depends on FFs’ data toggling correlations and probabilities. These naturally lead to optimal matching and exact covering problems. We present three problems arising by different clock-gating techniques. In a method called data-driven clock-gating, the corresponding covering problem is intractable but can practically be solved by appropriate heuristics. In another method called multi-bit flip-flops, the covering problem is easily solvable in a closed-form, required only sorting. We finally present the covering problem arising in a new method called look-ahead clock-gating, for which the question of whether the exact covering problem is easy or difficult is left open.

RECONFIGURABLE LOW POWER ARCHITECTURE FOR FAULT TOLERANT PSEUDO-RANDOM NUMBER GENERATION

High operating speed, fault tolerance (FT), low power and reconfiguration become today dominant issues during development and design of linear feedback shift registers (LFSRs), used as sequence generators, with randomness properties, in a process of testing complex CMOS VLSI ICs. In our design solution, we accomplish FT by using triple modular redundancy (TMR), i.e., a hardware scheme that uses spatial redundancy. For reduction of dynamic power consumption, clock-gating technique, as a simple and effective method, is implemented. The reconfigurable FPGA architecture provides us a feature to program and configure the degree of the primitive polynomial that the LFSR uses. High speed of operation, over 100 MHz, during testing is achieved by using circuits fabricated in submicron technology. An architecture which integrates in a single structure (IP core) all aforementioned design issues, named fault tolerant reconfigurable low-power pseudo-random number generator (FT_RLRG), is described in this article. The design of FT_RLRG is of practical interest in testing triple modular FT systems in the presence of single event upsets (SEUs), especially in a case when the design is SRAM-based. As an IP core the FT_RLRG has been implemented both on FPGA and ASIC technology. The main idea was to design a low-cost and low-power hardware structure which is able to adjust to any standards (past, present and future) operating at high-speed with different polynomials (currently up to 32nd order). The performance of FT_RLRG in respect to speed of operation (up to 150 MHz for FPGA and ASIC designs), low hardware overhead (0.033 mm2 area for ASIC and up to 530 slices for FPGA) and low-power consumption (0.45 mW for ASIC), for three different FPGA architecture (Spartan-3E, Virtex-4 and Virtex-6LP) and as an ASIC design implemented in 130 nm SiGe BiCMOS technology, have been estimated.

Low Power Reduced Instruction Set Architecture Using Clock Gating Technique

Low Power Reduced Instruction Set Architecture Using Clock Gating Technique

Skew Management of NBTI Impacted Gated Clock Trees

Negative bias temperature instability (NBTI) has emerged as the dominant failure mechanism for PMOS devices in nanometer integrated circuit (IC) designs, thus limiting their lifetime. There are several existing research works that mitigate impact of NBTI on gate delay and reliability. However, its impact on one of the most important components of modern IC design-the clock tree-has not been researched enough. Clock gating impacts the extent of NBTI-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> degradation of clock buffers leading to nonuniform NBTI degradation and, thus, increased clock skew. In this paper, we propose a practical design-time technique of modifying the clock gating implementation by selecting NAND or NOR gate as output stage of integrated clock gating cells with the objective of minimizing NBTI-induced clock skew. This selection intelligently modulates the signal probability and delay equations of clock signal paths with no extra hardware penalty. We formulate the skew minimization problem as an integer linear program which determines the optimal NAND or NOR assignment of clock gating buffer. Experimental results demonstrate the effectiveness of our method as the NBTI-induced clock skew is reduced by more than 74% compared to the traditional method. The impact of voltage and temperature variation on the proposed technique was analyzed and we observed reduced but still significant reduction in clock skew under variation as compared to the traditional clock gating technique.

Clock Gating Aware Low Power ALU Design and Implementation on FPGA

This paper deals with the design and implementation of a Clock Gating Aware Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, we analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques. On simulator, we achieved 88.23% clock power reduction using latch based clock gating and 70.58% clock power reduction using latch free clock gating. Index Terms—Clock gate, ALU, FPGA, LUT, clock power, register transfer level, dynamic power, leakage power

Low power clock gating techniques for synchronous buffer-based queue for 3D MPSoC

The buffer plays an important role in the design of MPSoC. The buffer mechanism influences the efficiency of link bandwidth. The buffer also provides a mechanism to synchronise the speed between the routers. The buffers are used to store packets or flits when they cannot be forwarded right away onto the output port. This paper presents discussion on buffering techniques used in the design of MPSoC. We have designed a synchronous queue for 3D MPSoC which could perform read and write operation at same time. We have generated full and AlmostFull signal to avoid overflow. The AlmostFull signal will be HIGH when one location is EMPTY to write data. The AlmostFull and full signal eliminates the overhead of sending credit information at every cycle. This reduces power dissipation from buffers. This paper presents four different low power techniques that are used to design memory for synchronous buffer-based queue.

A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme

In the Advanced Video Coding (AVC) standard, motion estimation (ME) adopts many new features to increase the coding performances such as block matching algorithm (BMA), motion vector prediction (MVP) and variable block size motion estimation (VBSME). However, VBSME is utilized in the MPEG4-AVC/H.264 standard which leads to high computational complexity and data dependency that make the hardware implementation very complex.This paper proposes a flexible VLSI architecture for full-search VBSME (FSVBSME), allowing the partitioning of the source frames into sixteen 4×4 sub-blocks and using a MVP scheme. A clock gating technique based on a distributed control unit is used for power saving. The proposed architecture was designed by Synopsys Design Compiler with 0.13μm CMOS standard cell library. Under a clock frequency of 500MHz, it allows a power consumption of about 131mW. Our VLSI architecture, compared with contemporary ones, can offer higher processing speed, lower power consumption, lower latency and lower gate count complexity.

Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms

This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypto processor. This approach results in processor that meets power consumption and performance specification for security applications. Proposed Implementation approach concludes higher system performance while reducing operating power consumption. Testing results shows that the MIPS crypto processor operates successfully at a working frequency of 218MHz and a bandwidth of 664Mbits/s.

Design of Low Power RISI Processor by Applying Clock Gating Technique

Power has become a primary consideration during hardware design. Dynamic power can contribute up to 50% of the total power dissipation. Clock-gating is the most common RTL optimization for reducing dynamic power. By applying Effective clock-gating technique on RISC processor adds additional logic to the existing synchronous circuit to prune the clock tree, thus disabling the portions of the circuitry that are not in use. Here in this project designed and developed efficient RISC CPU Interrupt controller unit ,Port controller and Program Flow Controller of an RISC Processor and clock gating technique applied to designed units. Combinational and Sequential clock-gating selectively suspend clocking while the block continues to produce output. In typical designs, combinational clockgating can reduce dynamic power by about 15-to20%.On the other hand sequential clock-gating can save significant power, typically reducing switching activity by 10-to-25% on a given block. Thus, different RTL techniques are used to reduce the power dissipation of a processor. The whole project captured in VHDL and implemented on targeted FPGA chip and observed the power using Xilinx Xpower tools.

Fault Secure Encoder and Decoder with Clock Gating

This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to reduce power consumption. A fault secure Encoder and Decoder error free low power logic circuits can be achieved by the proposed design. Simulation results show great improvement in power consumption. Fault secure Encoder and Decoder with clock gated by CG-element consumes approximately half the power of that consumed by the fault free circuit which doesn’t employ clock gating technique

LOW POWER ENCRYPTED MIPS PROCESSOR BASED ON AES ALGORITHM

The paper describes the Low power 32-bit encrypted MIPS processor based on AES algorithm and MIPS pipeline architecture. The pipeline stages of MIPS processor are arranged in such a way that pipeline can be clocked at high frequency and clock gating technique is used for reducing power consumption. Encryption blocks of Advanced Encryption Standard (AES) cryptosystem and dependency among pipeline stages are explained in detail with the help of block diagram. In order to reduce the power consumption, especially for portable devices and security application switching activity is used inside pipeline stages. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The encrypted MIPS pipeline processor can work at 210MHz and power consumption is 1.313W.

Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors

We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1.2 V, it dissipates 186 μW.

Power-efficient decoder implementation based on state transparent convolutional codes

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

Design and Implementation of a Low Power RSA Processor for Smartcard

Power consumption limits the application of public key cryptosystem in portable devices. This paper proposes a low power design of 1,024-bit RSA. In algorithm, the Chinese Remainder Theorem (CRT) and an improved Montgomery algorithm are selected to decrease the computation of RSA. In architecture and circuit, the operand isolation technique is applied to avoid unnecessary flip-flops of the combinational logic, and the clock gating technique is used to reduce the power dissipation of the registers. The proposed design is functionally verified on Altera FPGA EP2C8Q208C8N device. With SMIC 0.18μm CMOS process, the Synopsys synthesizing result shows that the area and the critical path are 7.1k gates and 5.3ns respectively, while the power is 2.56mW and the throughput can reach 49 kbps. Thus the proposed design requires lower power than previous designs.

A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video

H.264/AVC intra-frame encoding contains several computation-intensive coding tools that form a long data dependency loop that is difficult to speed up. In this paper, we present a low-power and high-performance H.264/AVC intra-frame encoder. We propose several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate an efficient CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized into a TSMC 0.13 μm CMOS cell library, our design requires 265.3 K gates at 114 MHz and consumes 23.56 mW to encode 1080pHD (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. Compared with all state-of-the-art designs, our design has a lower working frequency and achieves both better bit-rate saving and lower power consumption.

Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC

Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation.

A Novel Implementation of RISI Controller Employing Adaptive Clock Gating Technique

With the scaling of technology and the need for higher performance and more functionality power dissipation is becoming a major issue for controller design. Interrupt based programming is widely used for interfacing a processor with peripherals. The proposed architecture implements a mechanism which combines interrupt controller and RIS (Reduced Instruction Set) CPU (Central processing unit) on a single die. RISI Controller takes only one cycle for both interrupt request generation and acknowledgement. The architecture have a dynamic control unit which consists of a program flow controller, interrupt controller and I/O controller. Adaptive clock gating technique is used to reduce power consumption in the dynamic control unit. The controller consumes a power of 174µw@1MHz and is implemented in verilog HDL using Xilinx platform

모바일 기기 신호 인터페이스용 MIPI 디지털 D-PHY의 저전력 설계

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using CMOS process under 1.2V supply.

Power Optimized ALU for Efficient Datapath

With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. Also clock power can be significant in high performance systems. In this paper, a low power ALU for efficient datapath is proposed. In ALU, based on the observation, that while one functional unit is working other functional units remain idle, but they are connected to clock and all units dissipating significant amount of power. By using clock gating technique, a significant amount of power saving can be achieved at high frequency operations. Functionality of proposed ALU implemented on FPGA is tested using Xilinx tool. Power analysis is carried out using Xilinx’s Xpower analysis tool. It is found that designed ALU is dissipating a power of 24mw when it is operated at a clock frequency of 15MHz and supply voltage of 2.4V under load current of 4.8mA

ILP-based Computer-aided Testing and Optimization of Embedded Core

Low power consumption in a digital circuit can be achieved by partitioning it into sub-circuits which can be turned off at their inactive states. State encoding process can also reduce the power requirement considerably. Switching activity in a sequential logic circuit can be effectively reduced by Clock-gating techniques. In this work, the given circuit is modeled as finitestate machine and its decomposition is formulated into submachine as an Integer Linear Programming (ILP) problem. The power consumption is further reduced by a simple, but powerful state encoding method. The original circuit is decomposed into two structural sub circuits. Computer Aided Testing (CAT) environment is strategically applied in testing each of this sub circuit successively. The average power consumption resulted from the switching activity time interval is minimized by the process of partitioning the circuit and test session planning. In order to reduce the average switching activity, the small cluster of states having high stationary state probability is sought out, for creating the small sub-finite state machine.