Clock Delay Research Articles

Design of novel carry save adder using quantum dot-cellular automata

Complex adder designs in Quantum Dot-Cellular Automata (QCA) are primary focus of researchers on lowering cell-count, delay and QCA gates. The cell count, area and delay of two input adders such as Brent-Kung, Ladner-Ficher, Han-Carlson and Kogg-Stone are at least doubles when three numbers are added, compared to adding two numbers. Besides, the interconnected QCA wires for these adders decrease the addition time. To eliminate this problem, a new 4-bit Carry Save Adder (CSA) is proposed in this paper. To design the CSA circuit, a novel design of full adder circuit using 5-input majority gate (MV) has been proposed. The proposed design has around 11.76% improvement in cell count and 33.33% improvement in latency compared to the existing QCA full-adders. Besides, when three binary numbers are added, CSA is far more advantageous compared to similar addition using two input prefix adders, in terms of QCA cell count, area and clock delay. Compared to 4-bit traditional adders, proposed CSA has around 80% decreases in overall circuit cost. The QCA layout of CSA is the first one of its kind. An improved QCA layout of a 4-bit ripple carry adder (RCA) is also proposed in this paper. The RCA has around 7.6% improvement in cell count, 33.33% improvement in latency and around 5.56% improvement in overall cost over compared to the existing layouts.

Sequential circuit design using quantum-dot cellular automata

Quantum-Dot Cellular Automata (QCA) as technology is a promising candidate that has tremendous potential to replace CMOS due to its outstanding features such as low-power, extremely high density, fast operation speed. This paper presents a comprehensive research for design of sequential circuits using QCA. The study comprehends portrayal of D-type FF device in QCA as an embedded binary wire. Distinctive constraints and requirements for timing of sequential circuits in QCA are explored. An algorithm based on stretching of paths that takes into account the topological sorted order of vertices of directed acyclic graph is presented for assigning proper clock zones and matching clock delays. The S27 circuit from the ISCAS89 sequential benchmark set is considered as case study for implementation in multilayer QCA using the proposed algorithm.

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.

基于光脉冲位置调制的异步时钟错位采样数据恢复技术

基于光脉冲位置调制的异步时钟错位采样数据恢复技术

Optimum stochastic modeling for GNSS tropospheric delay estimation in real-time

In GNSS data processing, the station height, receiver clock and tropospheric delay (ZTD) are highly correlated to each other. Although the zenith hydrostatic delay of the troposphere can be provided with sufficient accuracy, zenith wet delay (ZWD) has to be estimated, which is usually done in a random walk process. Since ZWD temporal variation depends on the water vapor content in the atmosphere, it seems to be reasonable that ZWD constraints in GNSS processing should be geographically and/or time dependent. We propose to take benefit from numerical weather prediction models to define optimum random walk process noise. In the first approach, we used archived VMF1-G data to calculate a grid of yearly and monthly means of the difference of ZWD between two consecutive epochs divided by the root square of the time lapsed, which can be considered as a random walk process noise. Alternatively, we used the Global Forecast System model from National Centres for Environmental Prediction to calculate random walk process noise dynamically in real-time. We performed two representative experimental campaigns with 20 globally distributed International GNSS Service (IGS) stations and compared real-time ZTD estimates with the official ZTD product from the IGS. With both our approaches, we obtained an improvement of up to 10% in accuracy of the ZTD estimates compared to any uniformly fixed random walk process noise applied for all stations.

High-performance multiplexer architecture for quantum-dot cellular automata

The quantum-dot cellular automata (QCA) technology is a promising alternative technology to CMOS technology to extend the exponential Moore's law progress of microelectronics at nanoscale level, which is expected to be beneficial for digital circuits. This paper presents and evaluates three multiplexer architectures: a new and efficient 2:1 multiplexer architecture, a 4:1 multiplexer architecture, and 8:1 multiplexer architecture in the QCA technology. The 4:1 and 8:1 QCA multiplexer architectures are proposed based on the 2:1 QCA multiplexer. The proposed architectures are implemented with the coplanar crossover approach. These architectures are simulated using the QCADesigner tool version 2.0.1. The 2:1, 4:1, and 8:1 QCA multiplexer architectures utilize 15, 107, and 293 cells, respectively. The simulation results demonstrate that the proposed QCA multiplexer architectures have the best performance in terms of clock delay, circuit complexity, and area in comparison with other QCA multiplexer architectures.

Static Coulomb stress load on a three‐dimensional rate‐and‐state fault: Possible explanation of the anomalous delay of the 2004 Parkfield earthquake

AbstractWe perform quasi‐dynamic modeling of earthquake cycle using laboratory derived rate‐and‐state laws of friction on a homogeneous three‐dimensional fault model. We study effects of the static Coulomb stress loading on clock advance and clock delay of the subsequent event. We carefully investigate dependences of the clock advance on the onset time of the stress load, its amplitude, areal extent, and place of application of the load. We find that these dependences are complex, being controlled by the actual ongoing slip velocity on the fault, especially at the domain of the stress load. In particular, the stress (un)load can initiate the occurrence of quasiperiodic creep‐like episodes, which could be associated with episodic increases of microseismicity on real faults, such as observed on the locked Parkfield segment of the San Andreas Fault. Depending on the load parameters including its timing within the earthquake cycle, one of such creep‐like events may trigger the next (clock advanced) system‐size earthquake. In some cases, the nucleation of the main shock can fail, and the fault experiences one or several seismic events of smaller magnitudes instead. In such a case the next main shock becomes significantly delayed. We speculate that such mechanism could have contributed to the extreme delay of the M6 2004 Parkfield earthquake. Indeed, the Parkfield segment was subject to Coulomb stress unload due to the 1983 Coalinga‐Nuñez earthquakes and then experienced M4.9 events in 1993–1994, when the system‐size event was expected. Instead, these failed main shock nucleations delayed the Parkfield earthquake by another ~10 years.

Universal shift register implementation using quantum dot cellular automata

Abstract Quantum-dot Cellular Automata (QCA) demands to be a promising alternative of CMOS in ultra large scale circuit integration. Arithmetic and logic unit designs using QCA are of high research interest. A layout of four and eight bit universal shift register (USR) has been proposed. Initially QCA layouts of D flip-flop with clear and 4 to 1 multiplexer are designed, which are extended to design 4 and 8-bit parallel in parallel out (PIPO) shift register. Finally the PIPO is utilized to design 4-bit and 8-bit USR. By the comparative analysis it is observed that the proposed D Flip-flop achieved 40% clock delay improvement, whereas the modified layout of 4 to 1 multiplexer achieved 30% cell count reduction and 17% clock delay reduction from the previous works. This results in 31% reduction in cell count, 45% reduction in area and 55% reduction in clock cycle delay in 8 bit USR layout.

DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain

Physical unclonable function (PUF) has emerged as an attractive primitive to address diverse hardware security issues in integrated circuits, such as authentication and cryptographic key generation. Most of the existing PUFs rely on dedicated circuit structure for generating random signatures. It often causes concerns due to extra design efforts and hardware overhead. Moreover, the hardware complexity increases with higher entropy requirement, which may be unacceptable in area-constrained applications. In this paper, we propose DScanPUF, a novel PUF structure that leverages on the scan chain, a prevalent design-for-test structure in a chip. It is based on a low-overhead delay measurement structure consisting of a phase-locked loop and multiple clock delay lines to measure scan path delays at high resolution. A method is proposed to transform the responses into robust binary signatures. We note that the area of DScanPUF is only 18% of the ring-oscillator (RO) PUF with 1024 ROs. Moreover, it can be easily integrated into a design without any influence on testability. DScanPUF is evaluated with test results from 31 field-programmable gate array chips, which show good randomness, uniqueness and reproducibility under temperature, and supply voltage fluctuations. We also show that the signature is robust under aging effects on scan paths through a simulation at 45-nm CMOS process. Finally, we propose a simple structural modification to further improve the signature robustness.

Precise Clock Synchronization in the Readout Electronics of WCDA in LHAASO

The Water Cherenkov Detector Array (WCDA) is one of the key parts in the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered within a 90000 m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area, while a time measurement resolution better than 0.5 ns is required in the readout electronics. To achieve such time measurement precision, high quality clock distribution and synchronization among the 400 FEEs (each FEE for 9 PMTs readout) is required. To simplify the electronics system architecture, data, commands, and clock are transmitted simultaneously through fibers over a 400-m distance between FEEs and the Clock and Data Transfer Modules (CDTMs). In this article, we propose a new method based on the White Rabbit (WR) to achieve completely automatic clock phase alignment between different FEEs. The original WR is enhanced to overcome the clock delay fluctuations due to ambient temperature variations. This paper presents the general scheme, the design of prototype electronics, and initial test results. These indicate that a clock synchronization precision better than 50 ps is achieved over 1 km fibers, which is well beyond the application requirement.

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes

Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(nlogn) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be allocated with continuous delay of ADBs and (2) enables solving the ADB allocation problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB allocation to further reduce the ADBs to be used. The experimental results on benchmark circuits show that compared to the results produced by the best known ADB allocation algorithm, our proposed algorithm uses, on average under 30–50ps clock skew bound, 13.5% and 15.8% fewer numbers of ADBs for continuous and discrete ADB delays, respectively. In addition, when buffer sizing is integrated, our algorithm uses 31.7% and 31.3% fewer numbers of ADBs, even reducing the area of ADBs and buffers by 15.0% and 16.3% for continuous and discrete ADB delays, respectively.

LTE turbo decoder design**Project supported by the LTE-Advanced User Equipment Software Baseband Technology Major Project of China (No. 2013ZX0300315001).

This paper presents a turbo decoder supporting all 188 block sizes in 3GPP long term evolution (LTE) standard which can be employed in the LTE micro-eNodB system. The design allows 1, 2, 4, 8 or 16 soft-in/soft-out (SISO) decoders to concurrently process each block size, and the number of iterations can be adjusted. By adding a register in core structure add-compare-select-add, this article proposes an improved SISO algorithm and interleaving design, calculated forward state matrix and backward state matrix alternately, and the branch transition probability can be used in the Turbo decode process directly just after one clock delay. The structure enables a decoder processing radix-2 algorithm with high speed, instead of radix-4 as the conventional decoder. Moreover, the paper details an interleaver/de-interleaver, which is combined by two operational steps. One is column address mapping and the other is intra-row permutation. Decoder realizes interleaving by loading data from memories whose address is generated by column mapping and then lets data passing through inter-row permutation. For de-interleaving, the system can adopt reverse operation.

IMPLEMENTATION OF ARITHEMATIC OPERATIONS USING VEDIC MATHEMATICS

Abstract Vedic maths is the ancient Indian mathematics, it has 16 sutras for the calculations. These sutras can be used to solve very complex equation and operations. This paper seeks to present an integrated approach to implement the ALU using Vedic methods wherein the sutras are chosen and implemented for performing the basic operations like addition, subtraction, multiplication and logical operations. Sutras from vedic mathematics are selected according to the operations being performed and the verilog code is written and simulated for their implementation. The logical proof and explanation for the sutra’s application is given in detail. These sutras are completely based on logical and rational reasoning. The sutras used in this paper for implementation of above mentioned operations are all for general case. The timing report is generated showing minimum period, input arrival time before clock, maximum output required time after clock and maximum combinational path delay.

An Analog-Digital Clock DLL Control Circuit Used for High-Speed High-Resolution Digital-to-Analog Converter

An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) carefully. The proposed circuit is implemented in 0.18μm CMOS technology. Simulation results show that the proposed circuit performs well in various conditions in high speed data transmission applications.

Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails

This paper presents Razor-Lite, which is a low-overhead register for use in error detection and correction (EDAC) systems. These systems are able to eliminate timing margins by using specialized registers to detect setup time violations. However, these EDAC registers incur significant area and energy overheads, which mitigates some the system benefits. Razor-Lite is a new EDAC register that addresses this issue by adding only 8 additional transistors to a conventional flip-flop design. The Razor-Lite flip-flop achieves low overhead via a charge-sharing technique that attaches to a standard flip-flop without modifying its design. Side-channels connected to the floating nodes generate error flags through simple logic gates totaling 8 transistors, enabling register energy/area overheads of 2.7%/33% over a conventional DFF, while also not incurring extra clock or datapath loading or delay. Razor-Lite is demonstrated in a 7-stage Alpha architecture processor in a 45nm SOI CMOS technology with a measured energy improvement of 83% while incurring a 4.4% core area overhead compared to a baseline design.

Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling

Clock skew scheduling is an effective technique to improve the performance of sequential circuits. However, with process variations, it becomes more difficult to implement a large number of clock delays in a precise manner. Multidomain clock skew scheduling (MDCSS) is one way to overcome this limitation. In this paper, we prove the NP-completeness of multidomain clock scheduling problem and design a practical optimal algorithm to solve it. Given the domain number, we bound the number of all possible skew assignments and develop an optimal algorithm with efficient pruning techniques as well as a very efficient heuristics based on the optimal framework. The experimental results on ISCAS89 sequential benchmarks show the optimality and efficiency of our method compared with the most recent approaches to MDCSS.

Estimation of azimuthal anisotropy in the NW Pacific from seismic ambient noise in seafloor records

We analysed background surface waves in seismic ambient noise by cross-correlating continuous records of eight ocean bottom seismometers and nine differential pressure gauges deployed in the northwestern Pacific Ocean by the PLATE project. After estimating the clock delay and instrumental phase responses of differential pressure gauges by using cross-correlation functions, we measured average phase velocities in the area of the array for the fundamental-, first higher- and second higher-mode Rayleigh waves, and the fundamental-mode Love waves at a period range of 3–40 s by waveform fitting. We then measured phase-velocity anomalies of fundamental-mode and first higher-mode Rayleigh waves for each pair of stations at a period range of 5–25 s, and corrected the effect of variation in water-depths. The seismic anomalies imply the presence of strong azimuthal anisotropy beneath the eastern part of array. The direction of maximum velocity is approximately N35°E in the fossil seafloor spreading direction perpendicular to magnetic lineations from the ancient triple junction at this location. The peak-to-peak intensity of shear-wave velocity anisotropy in the mantle is ∼7 per cent.

Real‐time GPS sensing of atmospheric water vapor: Precise point positioning with orbit, clock, and phase delay corrections

AbstractThe recent development of the International Global Navigation Satellite Systems Service Real‐Time Pilot Project and the enormous progress in precise point positioning (PPP) techniques provide a promising opportunity for real‐time determination of Integrated Water Vapor (IWV) using GPS ground networks for various geodetic and meteorological applications. In this study, we develop a new real‐time GPS water vapor processing system based on the PPP ambiguity fixing technique with real‐time satellite orbit, clock, and phase delay corrections. We demonstrate the performance of the new real‐time water vapor estimates using the currently operationally used near‐real‐time GPS atmospheric data and collocated microwave radiometer measurements as an independent reference. The results show that an accuracy of 1.0 ~ 2.0 mm is achievable for the new real‐time GPS based IWV value. Data of such accuracy might be highly valuable for time‐critical geodetic (positioning) and meteorological applications.

Clock-Gating Approach to Low Power Domino Circuit Synthesis

Domino logic is often the choice for designing high speed CMOS circuits. Switching of gates in such a CMOS circuit, account for much of its dynamic power dissipation. Power minimization techniques like clock-gating, energy recovery clock, power gating and so on have limitations namely penalty on clock delay, logic overhead, synchronization issues and so on. In this work, we propose a method for implementing clock-gating to a Domino logic-based circuit, using a pattern recognition approach. For a given Domino circuit, first we identify a list of favourable gate patterns (FGPs) that can undergo clock-gating. Next, based on a graph-matching algorithm, we map these FGPs to the circuit elements achieving savings in power and area. Finally, we find an optimum set of patterns so that maximum power savings can be obtained with a minimum penalty on area. We have tested the efficacy of our approach with a set of standard benchmark circuits. Our proposed clock-gating approach offered 15% improvement in power savings and 18% improvement in area penalty compared to the existing work.

Radiation hard programmable delay line for LHCb calorimeter upgrade

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.