Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes

Abstract

Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(nlogn) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be allocated with continuous delay of ADBs and (2) enables solving the ADB allocation problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB allocation to further reduce the ADBs to be used. The experimental results on benchmark circuits show that compared to the results produced by the best known ADB allocation algorithm, our proposed algorithm uses, on average under 30–50ps clock skew bound, 13.5% and 15.8% fewer numbers of ADBs for continuous and discrete ADB delays, respectively. In addition, when buffer sizing is integrated, our algorithm uses 31.7% and 31.3% fewer numbers of ADBs, even reducing the area of ADBs and buffers by 15.0% and 16.3% for continuous and discrete ADB delays, respectively.