Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails

Abstract

This paper presents Razor-Lite, which is a low-overhead register for use in error detection and correction (EDAC) systems. These systems are able to eliminate timing margins by using specialized registers to detect setup time violations. However, these EDAC registers incur significant area and energy overheads, which mitigates some the system benefits. Razor-Lite is a new EDAC register that addresses this issue by adding only 8 additional transistors to a conventional flip-flop design. The Razor-Lite flip-flop achieves low overhead via a charge-sharing technique that attaches to a standard flip-flop without modifying its design. Side-channels connected to the floating nodes generate error flags through simple logic gates totaling 8 transistors, enabling register energy/area overheads of 2.7%/33% over a conventional DFF, while also not incurring extra clock or datapath loading or delay. Razor-Lite is demonstrated in a 7-stage Alpha architecture processor in a 45nm SOI CMOS technology with a measured energy improvement of 83% while incurring a 4.4% core area overhead compared to a baseline design.