Classical Phase-locked Loop Research Articles

Computationally Efficient Finite-Position-Set-Phase-Locked Loop for Sensorless Control of PMSGs in Wind Turbine Applications

Finite-control-set model predictive control (FCS-MPC) techniques have been widely applied for power electronics, and motor drive. Furthermore, the principles of FCS-MPC have been extended to phase-locked loop (PLL), which called finite-position-set PLL (FPS-PLL), for sensorless control of permanent-magnet synchronous generators (PMSGs) in wind turbine applications (WTAs). However, 64 iterations are essential to find the optimal rotor position, i.e., high computational burden. In this article, two computationally efficient (CE) FPS-PLLs are proposed for encoderless control of PMSGs in WTAs. The first CE-FPS-PLL $_1$ reduces the number of iterations to 36 with slightly better accuracy than the FPS-PLL, while the second (novel) CE-FPS-PLL $_2$ calls for only 24 iterations to find the best rotor position with significantly better accuracy than the FPS-PLL. The performance of the proposed CE-FPS-PLLs has been experimentally investigated, and compared with that of the FPS-PLL, and classical PLL using a 14.5-kW PMSG. Furthermore, the robustness of the proposed CE-FPS-PLLs is investigated against variations of the PMSG parameters.

Direct Phase-Angle Detection for Three-Phase Inverters in Asymmetrical Power Grids

This article introduces a signal reformation-based direct phase-angle detection (DPD-SR) technique for three-phase inverters supporting asymmetrical grids. Asymmetries in three-phase systems may happen because of unbalanced three-phase loads, which can lead to the voltage asymmetry at the terminals of grid-tied inverters. The proposed DPD-SR technique can detect the voltage phase angle under asymmetrical conditions. The DPD-SR technique also offers precise and rapid phase-angle detection through signal reformation and trigonometric functions. In essence, the phase-angle detection is directly derived from the trigonometric properties of the line–line voltages, while signal reformation is implemented to handle asymmetrical voltages. The proposed method measures two line–line voltages and detects the phase angle of a three-phase system under both symmetrical and asymmetrical conditions. Unlike classical phase-locked loop (PLL) techniques, DPD-SR does not need any closed-loop proportional-integral (PI) controller, which significantly reduces the complexity and the delay in detecting the phase angle. In this article, the efficacy of the proposed technique is examined in comparison with the state-of-the-art PLLs under asymmetrical conditions through a set of laboratory experiments. The performance of the phase-angle detection is also tested as part of an inverter feeding an asymmetrical grid.

Non-linear analysis of a modified QPSK Costas loop

A Costas loop is one of the classical phase-locked loop based circuits, which demodulates data and recovers carrier from the input signal. The Costas loop is essentially a nonlinear control system and its nonlinear analysis is a challenging task. In this article for a modified QPSK Costas loop we analyze the hold-in, pull-in and lock-in ranges. New procedure for estimation of the lock-in range is considered and compared with previously known approach.

Hold-in, Pull-in and Lock-in Ranges for Phase-locked Loop with Tangential Characteristic of the Phase Detector

In the present paper the phase-locked loop (PLL), an electric circuit widely used in telecommunications and computer architectures is considered. A new modification of the PLL with tangential phase detector characteristic and active proportionally-integrating (PI) filter is introduced. Hold-in, pull-in and lock-in ranges for given circuit are studied rigorously. It is shown that lock-in range of the new PLL model is infinite, compared to the finite lock-in range of the classical PLL.

Simulation and investigations of a software implemented phase-locked loop with improved noise immunity

The improvement of noise immunity of a communication system is an effective way to increase the capacity of communication systems, which would provide more qualitative service for a larger number of users. This task can be solved by lowering the noise threshold of a phase-locked loop (PLL) in these systems if the dynamic properties of the device are preserved. The literature review indicates that such a device with improved noise immunity has already been implemented, but the effects of noise and modulation on its dynamic behavior were analyzed separately. This article is devoted to the analysis of the behavior of a digital firmware PLL under the simultaneous influence of noise and modulation of the input signal. The article depicts the structure of the classical digital PLL and its modifications and explains key differences between them. The simulation of the classical PLL with either absence or presence of noise at the device input was carried out. The simulation results show that the PLL is not able to detect all phase changes when the noise is present. Besides, the modified PLL has a wider working frequency range than the classical one under noisy conditions. The investigations of the PLL dynamic behavior with the simultaneous influence of random noise and Binary Phase Shift Keying (BPSK) modulated input signal was performed. The results of the research show that the duration of the transient processes during the processing of the BPSK modulated signal in the modified device is at least twice as low as that for the classical one. In addition, the number of errors during the signal detection increases faster for the classical PLL than for the modified one when the noise level rises. The use of the modified PLL in modern communication systems gives an opportunity to increase their capacity.

Firmware implementation and experimental research of the phase-locked loop with improved noise immunity

This paper presents a method for improvement of the phase-locked loop (PLL) noise immunity by using a modified phase detector. The article shows structural diagram of the PLL with the modified phase detector and describes the criterion for choosing the parameters of the narrowband filter and the high-pass filter to prevent distortions of information signal. Simulation of both classical and modified devices was carried out to find a noise threshold, which causes phase-locked loop to unlock. Simulation results show that multiple cycle slips of synchronization in short period of time in modified PLL occur for higher levels of noise (by 1.5–4 dB depending on PLL parameters), than in classical PLL. Both devices were software implemented on FPGA (field programmable gate array) logic and experimental studies of their noise immunity were conducted. The results of experimental studies qualitatively correspond to simulation ones and show that the that noise threshold of the modified phase detector is greater up to 1–2.5 dB depending on the device parameters. Experimental research also shows that modified phase detector does not deteriorate the dynamic properties of whole device and even improves them in comparison to classical PLL.

Nonlinear analysis of hybrid phase-controlled systems in z-domain with convex LMI searches

Phase-controlled systems such as phase-locked loops (PLLs) have been used in numerous applications ranging from data communications to speed motor control. The hybrid case where only the phase detector is digital while others are analog has advantages over the classical PLLs in the sense that it provides a wider locking range and is more suitable when the input and output signals come in digital waveforms. Although such systems are inherently nonlinear due to the phase detector's characteristics, the nonlinearity is often bypassed in order to ease the analysis and design methods. This, however, will give erroneous results when the phase difference between input and output falls into the nonlinear range. Another source of inaccuracies in modeling PLLs is the continuous-time approximation, which is only useful if the operating frequencies of interest are much less than the incoming data transition rate. In this paper, we present a nonlinear analysis of a hybrid PLL in the z-domain where the stability is established via the discrete-time Lur'e-Postnikov Lyapunov function, and the performance is evaluated via the induced $\ell_2$ norm objective. The results are formulated in the form of linear matrix inequality searches, which are computationally tractable. We also extend the result for analysis of a PLL-based frequency synthesizer and provide several numerical examples to illustrate the effectiveness of the results compared to the existing ones.

The Phase-Locked Loop and Costas Loop

In this study, the classical phase-locked loop (PLL) and Costas loop are investigated together. How the synchronization is obtained by the carrier recovery from the sinusoidal reference signal is mathematically shown with some assumptions and presented. It is concluded from this paper that Costas loop produces about half of the error signal produced by the PLL in the locked-stateoperation. This result may affect the decision whether the Costas loop will be used more frequently in the phase coherent communication systems in the future.

Nonlinear analysis of PLL by the harmonic balance method: limitations of the pull-in range estimation.

In this paper we discuss the application of the harmonic balance method for the global analysis of the classical phase-locked loop (PLL) circuit. The harmonic balance is non rigorous method, which is widely used for the computation of periodic solutions and the checking of global stability. The proof of the absence of periodic solutions is a key step to establish the global stability of PLL and estimate the pull-in range (which is an interval of the frequency deviations such that any solution tends to one of the equilibria). The advantages and limitations of the study of the classical PLL with lead-lag filter using the harmonic balance method is discussed.

Simulation of the classical analog phase-locked loop based circuits

In this paper a short survey on the simulation of classical phase-locked loop based circuits (PLLs) is presented. Nonlinear models of PLLs with mixer/multiplier phase detector are considered. Computation of phase detector characteristics for non-harmonic and non-squarewave signals is discussed.

A new on-line bandwidth tuning approach for biquad OTA-C filters

A new and general bandwidth (BW) tuning strategy for biquad OTA-C filters is presented. We have taken benefit of the advantages of the classical Phase-Locked Loop (PLL) scheme to on-line tune the central frequency fo and we have applied it to tune also the bandwidth BW of biquad filters. The proposed design procedure uses only two different sizes of OTAs. This methodology has been applied to five biquad band-pass OTA-C filters, allowing fo-tuning and BW-tuning in an independent way. Furthermore, the influence of OTA non-idealities is discussed by including compact and general expressions for fo and BW for all these filters. Simulation results validate our proposal with excellent BW-tuning accuracies: an rms error of 0.73% with respect to the bandwidth desired.

Nonlinear analysis of classical phase-locked loops in signal's phase space

Discovery of undesirable hidden oscillations, which cannot be found by the standard simulation, in phase-locked loop (PLL) showed the importance of consideration of nonlinear models and development of rigorous analytical methods for their analysis. In this paper for various signal waveforms, analytical computation of multiplier/mixer phase-detector characteristics is demonstrated, and nonlinear dynamical model of classical analog PLL is derived. Approaches to the rigorous nonlinear analysis of classical analog PLL are discussed.

Nonlinear analysis of phase-locked loop with squarer

The phase-locked loop with squarer is a classical phase-locked loop (PLL) based carrier recovery circuit. Simulation of the loop is nontrivial task, because of high-frequency properties of considered signals. Simulation in space of signals’ phases allows one to overcome these difficulties, but it is required to compute phase detector characteristic. In this paper for various waveforms of high-frequency signals new classes of phase detector characteristics are computed for the first time. The problems of rigorous mathematical analysis of the control signal of voltage-controlled oscillator are discussed. Nonlinear model of PLL with squarer is constructed.

Phase-Locked Loop Based on Selective Harmonics Elimination for Utility Applications

Phase-locked loops (PLL) are widely used in power electronics equipment connected to the mains. The use of a square wave voltage-controlled oscillator instead of a sinusoidal one eliminates one multiplier, resulting in a simple PLL algorithm, suitable for low-cost processors. In spite of its simplicity, distorted grid voltages cause steady-state phase error. This paper proposes the use of a modified square waveform obtained by the selective harmonics elimination (SHE) method to solve the phase error problem. Simulation and experimental results for the steady state and the transient tests are presented to validate the proposed single-phase and three-phase SHE-PLL methods. The tests using a field-programmable gate array show that the dynamic response of the proposed method is similar to that of classical PLL, with a simpler implementation.

Analytical Method for Computation of Phase-Detector Characteristic

Discovery of undesirable hidden oscillations, which cannot be found by simulation, in models of phase-locked loop (PLL) showed the importance of development and application of analytical methods for the analysis of such models. Approaches to a rigorous nonlinear analysis of analog PLL with multiplier phase detector (classical PLL) and linear filter are discussed. An effective analytical method for computation of multiplier/mixer phase-detector characteristics is proposed. For various waveforms of high-frequency signals, new classes of phase-detector characteristics are obtained, and dynamical model of PLL is constructed.

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

10-GHz clock recovery using an optoelectronic phase-locked loop based on three-wave mixing in periodically poled lithium niobate

Clock recovery is a critical function of any digital communications system. To replace the classical electronic phase-locked loops (PLLs) at higher bit rates, several all-optical or optoelectronic clock recovery methods are being studied. This letter presents an optoelectronic PLL where three-wave mixing in a periodically poled lithium niobate (PPLN) device provides the phase comparator. Since PPLN is passive, it generates no amplified spontaneous emission noise; also, the error signal is in the visible (763 nm), therefore easily separated from infrared input signals. Clock recovery is performed on a 10-GHz sinusoidal optical signal. Being based on ultrafast nonlinear effects, this scheme should be able to reach still higher bit rates, on the order of several hundred gigahertz. Also, subclock extraction (e.g., 40-to-10 GHz) should be possible without modifications.

Designing phase-locked loops for instrumentation applications

Many transducers provide a pulsed output whose frequency depends on the specific measurand’s property. Conversion of the signal from a frequency-analogue to provide a magnitude-analogue output requires an accurate estimate of frequency, which is difficult when there is significant noise. Two common approaches to this problem—zero-crossing (ZC) detection and phase-locked loops (PLL)—are analysed and compared. The classical PLL however has difficulty handling baseband signals, where the expected input frequency ratio is large. A carefully chosen PLL structure, using heterodyning and a Hilbert transform phase-sensitive detector, is shown to cope with input data having high noise and a wide spread of possible frequency. The corresponding PLL design equations are derived: these indicate the improvement in performance over that of a classical PLL, an all-digital PLL and a ZC algorithm.

Phase-locked operation of RSFQ ring oscillators

Ring oscillators are the traditional on-chip clock source for RSFQ mixed-signal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an A/D converter or the output clock of a D/A converter. However conventional bias schemes lead to excessive drift in the frequency. Embedding the ring oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit comprised of a ring oscillator, a divide-by-220 prescaler and a resynchronizer D flip-flop was fabricated using the standard 1 kA cm-2 niobium foundry service from Hypres. The circuit was stabilized using a low-frequency PLL with a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring oscillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscillator output was measured in open- and closed-loop configurations. Compared to the open-loop phase noise spectrum the closed-loop spectrum showed a decrease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the divided-down carrier frequency of 4.1 kHz. This agreed with the classical phase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz oscillator used as the reference in the PLL.

A 150-MHz translinear phase-locked loop

This paper describes the design and implementation of a current-mode phase-locked loop (PLL) using static and dynamic (log-domain) translinear circuits. The loop is fully tuneable, with independent control of center frequency and loop bandwidth. The loop employs a recently proposed current-mode "log-domain" oscillator in a classical PLL topology to obtain these features. The PLL has been fabricated in a 0.6-/spl mu/m 12-GHz BiCMOS process, and measured results show a capture range of 15 MHz at a center frequency of 150 MHz. The circuit operates from a single 3-V supply and draws 6 mA at 150 MHz. A phase noise of -80 dBc/Hz at 1 kHz offset was obtained with the PLL locked onto an input reference frequency of 151 MHz. The PLL response to a frequency-modulated input has also been examined, and the demodulated output at 100 KHz showed less than -30-dB total harmonic distortion.