Phase-Locked Loop Based on Selective Harmonics Elimination for Utility Applications

Abstract

Phase-locked loops (PLL) are widely used in power electronics equipment connected to the mains. The use of a square wave voltage-controlled oscillator instead of a sinusoidal one eliminates one multiplier, resulting in a simple PLL algorithm, suitable for low-cost processors. In spite of its simplicity, distorted grid voltages cause steady-state phase error. This paper proposes the use of a modified square waveform obtained by the selective harmonics elimination (SHE) method to solve the phase error problem. Simulation and experimental results for the steady state and the transient tests are presented to validate the proposed single-phase and three-phase SHE-PLL methods. The tests using a field-programmable gate array show that the dynamic response of the proposed method is similar to that of classical PLL, with a simpler implementation.