Firmware implementation and experimental research of the phase-locked loop with improved noise immunity

Abstract

This paper presents a method for improvement of the phase-locked loop (PLL) noise immunity by using a modified phase detector. The article shows structural diagram of the PLL with the modified phase detector and describes the criterion for choosing the parameters of the narrowband filter and the high-pass filter to prevent distortions of information signal. Simulation of both classical and modified devices was carried out to find a noise threshold, which causes phase-locked loop to unlock. Simulation results show that multiple cycle slips of synchronization in short period of time in modified PLL occur for higher levels of noise (by 1.5–4 dB depending on PLL parameters), than in classical PLL. Both devices were software implemented on FPGA (field programmable gate array) logic and experimental studies of their noise immunity were conducted. The results of experimental studies qualitatively correspond to simulation ones and show that the that noise threshold of the modified phase detector is greater up to 1–2.5 dB depending on the device parameters. Experimental research also shows that modified phase detector does not deteriorate the dynamic properties of whole device and even improves them in comparison to classical PLL.