class-D Power Amplifier Research Articles

Digital Signal Processing in Power Electronics Control Circuits, Second Edition [Book News

This textbook has been revised and extended for its second edition (the first edition was published in 2013). It discusses problems related to the design and implementation of digital control algorithms for power electronics systems using the digital signal processing (DSP) approach. The contents of the book are organized into seven chapters: 1) “Introduction” 2) “Analog Signals Conditioning and Discretization” 3) “Selected Methods of Signal Filtration and Separation and Their Implementation” 4) “Selected Simulation Methods and Programs for Power Electronic Circuits” 5) “Selected Active Power Filter Control Algorithms” 6) “Digital Signal Processing Circuits for Digital Class-D Power Amplifier” 7) “Conclusion and Future Work.” The book opens in Chapter 2 with a discussion on the processing of analog-to-digital (A/D) signals and the most common source of errors. The author presents an overview of A/D converters suitable for power electronics control. Digital filters, multirate circuits, digital filter banks, and microcontrollers for power electronics are discussed in Chapter 3. This second edition includes a new and useful Chapter 4 that presents problems pertaining to the simulation of digitally controlled power electronic systems and includes numerous program listings in MATLAB and PSIM. The next two chapters include descriptions of selected active power filter (Chapter 5) and class-D power amplifier control algorithms (Chapter 6) as well as their implementation, simulation, and experimental results. The book concludes with a summary and a midterm forecast for future research and developments. The contents of the book are easy to read and presented in an interesting way with good illustrations. Each chapter includes an extensive list of references. This book fills a gap between power electronics and digital signal processing. I strongly recommend it to engineering educators, graduate students, and industry engineers who are interested in understanding the design of modern DSP-controlled power electronic systems.

A Wideband All-Digital CMOS RF Transmitter on HDI Interposers With High Power and Efficiency

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied.

A Recursive Switched-Capacitor House-of-Cards Power Amplifier

A fully integrated CMOS power amplifier (PA) that efficiently generates high-voltage RF waveforms directly from a 4.8-V supply using only low-voltage thin-oxide transistors is introduced. High-voltage operation is achieved via implicit ~100% efficient dc–dc conversion enabled by stacking and flying individual class-D PA cells in a House-of-Cards (HoC) topology. By dynamically reconfiguring digitally controlled HoC slices to support different voltage conversion ratios and capacitively coupling their outputs, a Doherty-like high-efficiency backoff profile is achieved without using any magnetic impedance inverter. A test chip, implemented in 65-nm low-power CMOS, operates directly from 4.8 V using only 1.2-V transistors, and attains above 40% battery-to-RF efficiency at both 23-dBm peak power and at 6-dB backoff at 720 MHz. When applying a 10-MHz 16-quadrature amplitude modulation signal, the PA achieves an error vector magnitude of 3.6%-rms without using any predistortion techniques with an average output power and power-added efficiency of 15.7 dBm and 26.5%.

Low-Jitter GaN E-HEMT Gate Driver With High Common-Mode Voltage Transient Immunity

An improved gate driver is presented which significantly lowers the output noise of high-precision switch-mode (Class-D) power amplifiers by reducing signal jitter at the output of the power stage tenfold to values below 20 ps. Gate signal jitter in power electronic converters, which introduces wideband noise to the power output, originates mainly from the signal isolators that are required to provide the galvanically isolated gate driver control signals. A low-jitter gate control signal is produced by employing a digital flip-flop, which uses a low-jitter isolated clock, to resynchronize the jittery gate control signal. By utilizing the clock-enable input of the flip-flop, the gate driver can be rendered immune to high-speed common-mode transients, which is important as the Class-D power amplifier demonstrator system employs fast-switching GaN E-HEMT transistors, where the 400 V switching transients exceed 300 kV μs <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The signal to noise ratio of a sinusoidal output signal is measured at 107 dB, which is an improvement of ≈ 20 dB as compared to the performance of a conventional gate driver.

Wireless Power Transfer System With $\Sigma\Delta$- Modulated Transmission Power and Fast Load Response for Implantable Medical Devices

The Class-D power amplifier (PA) is widely used to drive the primary coil of wireless power transfer (WPT) systems. Due to coupling and loading variations, the PA is required to adjust the transmission power quickly, precisely, and efficiently. In this brief, a switching-frequency-modulation-based Sigma-Delta ( $\Sigma\Delta$ ) modulator is proposed for driving the PA with minimal hardware overhead. The control of the Class-D PA's output voltage at the fundamental tone is proved to be linear. Using a $\Sigma\Delta$ modulator, a WPT system is designed with a fast control loop for the voltage regulation of the receiver at the secondary coil. A transmitter chip and a receiver chip are fabricated using the AMS 0.35- $\mu\text{m}$ CMOS process. The $\Sigma\Delta$ modulator is implemented in a field-programmable gate array. The measurement results show that, with the proposed $\Sigma\Delta$ modulator, the tuning range of the receiver output voltage could be improved by 50% compared with the conventional one. The load transient response time is only 10 $\mu\text{s}$ .

A 40–170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS

A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used in pulsewidth modulation (PWM) generation. Multilevel signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high peak-to-average power ratios (PAPRs). A differential folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with an additional supply source/sink path compared with the 2-level operation. The PWM driver has been implemented in a 130 nm CMOS process and can operate with a switching frequency of 40–170 MHz. For the 2-/3-/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is −61/−62/−53 dB and the corresponding efficiency is 71%/83%/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2-/3-level PA with a high PAPR signal with 500 kHz bandwidth. While intended as a general-purpose amplifier, the approach is well-suited for applications such as power-line communications.

Soft‐switching single‐stage three‐level power amplifier for high‐voltage audio distribution systems

An isolated fully soft-switching single-stage three-level power amplifier (SS3L) based on dual auxiliary networks (DAN) is proposed in this Letter. Compared with the conventional class-D power amplifier, the proposed DAN-SS3L achieves high level of integration without bulky dc link capacitor, and high-efficiency by single-stage conversion and zero voltage switching for all the switches under different operating conditions from light load to full load, which is suitable for high-voltage audio distribution systems. By adopting active auxiliary network, the energy stored in the leakage inductor can be recycled, which eliminates the pulse width modulation voltage spikes. The passive auxiliary network provides enough reactive current for primary-side switches, extending soft-switching range. In addition, commutation overlap strategy is employed to enable natural commutation of bidirectional switches. Experimental results of a 200 W prototype are presented to verify the analysis results.

Design of a broadband current mode class-D power amplifier with harmonic suppression

Current mode class-D power amplifiers (CMCD-PA) are attractive for fully integrated PA implementation as the output capacitance of the active device can be absorbed in the output matching network that can be realized with minimum number of components. This paper presents a simplified design approach for CMCD PA design using an integrated balun transformers. Expressions are derived for the optimum device sizing for second harmonic suppression resulting in improved efficiency. An expression of amplifier efficiency as a function of device size is is presented proving that current mode class-D amplifier yields higher higher efficiency than a class-E amplifier for the same device size. The amplifier is implemented in 130 nm CMOS process and encapsulated in QFN package. Measurement results show that the amplifier exhibits broadband response between 1.4 and 2.1 GHz with peak output power of 26.8 dBm at 1.8 GHz using a 2.4 V supply. PAE remains above 40 % for the entire range while peak PAE is 48 %. Results show a good match between simulation and measurement work. Voltage sweep of the amplifier shows that it can be used in supply modulation based LINC techniques.

An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS

A 65-nm all-digital Class-S transmitter with an entire digital frontend (DFE) and a current-mode Class-D (CMCD) power amplifier (PA) is presented. To realize the high operation rate and performance of the DFE, which includes a 1-bit band-pass $\Sigma \Delta $ modulator, a mixer, and interpolation filters, approaches, such as time-interleaving algorithm and modified Manchester encoding, are adopted. The main blocks in the DFE are implemented using standard cells with electronic design automation tools for synthesis and place and route. A CMCD PA with an ON-chip transformer is designed and integrated. This Class-S transmitter exhibits a 40-MHz bandwidth at up to a 1.6 GHz output carrier frequency. Measurements with a 1-MHz channel-spacing $\pi $ /4 quadrature phase shift keying signal show a power control range of −18.66 to −4.65 dBm, and the power consumption of the $\Sigma \Delta $ modulator core is 7 mW.

A Digitally Intensive Transmitter/PA Using RF-PWM With Carrier Switching in 130 nm CMOS

A digitally intensive transmitter using RF pulse-width-modulation (PWM) with a class-D power amplifier (PA) is described. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs full carrier frequency for half of the amplitude range and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratios (PAPR) but also improves back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20 MHz 64-QAM OFDM signals, the average output power is 18.3 dBm and the PAE is 16% with an EVM of $-25.5\; \text{dB}$ .

A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

Modeling of nonlinear system based on deep learning framework

A novel modeling based on deep learning framework which can exactly manifest the characteristics of nonlinear system is proposed in this paper. Specifically, a Deep Reconstruction Model (DRM) is defined integrating with the advantages of the deep learning and Elman neural network (ENN). The parameters of the model are initialized by performing unsupervised pre-training in a layer-wise fashion using restricted Boltzmann machines (RBMs) to provide a faster convergence rate for modeling. ENN can be used to manifest the memory effect of system. To validate the proposed approach, two different nonlinear systems are used for experiments. The first one corresponds to the class-D power amplifier which operates in the ohmic and cutoff regions. According to error of time domain and spectrum, back propagation neural network model improved by RBMs (BP-RBMs) and ENN are compared with different input signals which are the simulated two-tone signal and actual square wave signal. The second system is a permanent magnet synchronous motor servo control system based on fuzzy PID control strategy. In terms of simulated and actual speed curves, BP-RBMs, DRM and ENN models are adopted on comparison, respectively. It is shown by experimental results that the proposed model with fewer parameters and iteration number can reconstruct the nonlinear system accurately and depict the memory effect, the nonlinear distortion and the dynamic performance of system precisely.

A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices

This paper presents a fractional-N phase-locked loop based spread spectrum clock generator (SSCG) using a programmable linear frequency modulator. The SSCG provides a programmable frequency deviation and modulation frequency regardless of its operating frequency. The ranges of frequency-deviation ratio and modulation frequency are 0–80% and 0–100 kHz with 610 Hz step resolution. The proposed SSCG successfully support five serial-link standards by using a single SSCG, and can be applied to various switching circuits such as class-D power amplifiers or switching power converters. The EMI reduction was measured to be 10.24–13.94 dB under 100-kHz resolution bandwidth. The proposed SSCG was fabricated using a 0.13-μm CMOS process with an active area of 0.11 mm2, while consuming an overall power of 6.28 mW at 1 GHz.

A High-Power CMOS Class-D Amplifier for Inductive-Link Medical Transmitters

Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used, thanks to their high efficiency at high frequencies. The initial specifications driving this study require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip (PLL) a dead-time generator and a phase detector. The PA was designed in a 0.18- $\mu$ m CMOS high-voltage process technology and occupies an area of 9.86 mm $^2$ . It works at frequencies up to 14 MHz and 30-V supply and efficiencies higher than 80 $\%$ are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimizes power delivery to medical implants.

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

This paper describes the power dissipation analysis and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented in a 0.14 $\mu$ m SOI BCD process, the amplifier achieves 93% efficiency at 45 W output power, ${>}80\hbox{\%}$ power efficiency down to 4.5 W output power and ${>}49\hbox{\%}$ efficiency down to 0.45 W output power.

A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners

In this paper, we present a 25 dBm Class-D outphasing power amplifier (PA) with cross-bridge combiners. The Class-D PA is designed in a standard 45 nm process while the combiner is implemented on board using lumped elements for flexibilities in testing. Comparing with conventional non-isolated combiners, the elements of the cross-bridge combiner are carefully chosen so that additional resonance network is formed to reduce out-of-phase current, thereby increasing backoff efficiency of the outphasing PA. The Class-D outphasing PA with the proposed combiner is manufactured and measured at both 900 MHz and 2.4 GHz. It achieves 55% peak power-added efficiency (PAE) at 900 MHz and 45% at 2.4 GHz for a single tone input. For a 10 MHz LTE signal with 6 dB PAR, the PAE is 32% at 900 MHz with −39 dBc adjacent channel power ratio (ACPR) and 22% at 2.4 GHz with −33 dBc ACPR. With digital predistortion (DPD), the linearity of the PA at 2.4 GHz is improved further to reach −53 dBc, −50 dBc, −42 dBc ACPR for 10 MHz, 20 MHz, and 2-carrier 20 MHz LTE signals.

A 13.56-mbps pulse delay modulation based transceiver for simultaneous near-field data and power transmission.

A fully-integrated near-field wireless transceiver has been presented for simultaneous data and power transmission across inductive links, which operates based on pulse delay modulation (PDM) technique. PDM is a low-power carrier-less modulation scheme that offers wide bandwidth along with robustness against strong power carrier interference, which makes it suitable for implantable neuroprosthetic devices, such as retinal implants. To transmit each bit, a pattern of narrow pulses are generated at the same frequency of the power carrier across the transmitter (Tx) data coil with specific time delays to initiate decaying ringing across the tuned receiver (Rx) data coil. This ringing shifts the zero-crossing times of the undesired power carrier interference on the Rx data coil, resulting in a phase shift between the signals across Rx power and data coils, from which the data bit stream can be recovered. A PDM transceiver prototype was fabricated in a 0.35- μm standard CMOS process, occupying 1.6 mm(2). The transceiver achieved a measured 13.56 Mbps data rate with a raw bit error rate (BER) of 4.3×10(-7) at 10 mm distance between figure-8 data coils, despite a signal-to-interference ratio (SIR) of -18.5 dB across the Rx data coil. At the same time, a class-D power amplifier, operating at 13.56 MHz, delivered 42 mW of regulated power across a separate pair of high-Q power coils, aligned with the data coils. The PDM data Tx and Rx power consumptions were 960 pJ/bit and 162 pJ/bit, respectively, at 1.8 V supply voltage.

Modeling based on Elman Wavelet Neural Network for Class-D Power Amplifiers

The Foundation of Key Laboratory of China’s Education Ministry and A Project Funded by the Priority Academic Program Development of Jiangsu Higher Education Institutions.

Self-oscillatory class-D power amplifiers with a hysteresis-free relay element

For a self-oscillatory class-D power amplifier, structural models and mathematical formulas are derived by the harmonic-balance method, in order to calculate the frequency and amplitude of self-oscillations and the mean processes occurring under the action of a slowly varying input signal. Formulas for the parameters of these models are determined. For the mean processes, the stability condition of the structural model is established. Transient processes in the amplifier are plotted in the case of constant and sinusoidal input signals, on the basis of a Matlab/Simulink model.

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a resolution of 1.4 ps (8 bit) required to meet WiFi requirements. A phase MUX architecture is proposed to implement switching between phases once every LO period (2.4 GHz) without generating detrimental glitches at the output. Due to its open-loop nature, the proposed phase modulator is capable of delivering wide OFDM bandwidths up to 40 MHz. The paper analyzes the impact of impairments, e.g., delay mismatch within the delay cells and outphasing mismatches, as well as associated mitigation techniques. The transmitter has been implemented in a 32-nm digital CMOS process and delivers an OFDM average power of 20 dBm with an overall system efficiency of 18.6% when transmitting 54-Mb/s 64QAM signal. The fully digital design is expected to further improve in power dissipation and chip-area with further CMOS scaling.