Abstract
This paper describes the power dissipation analysis and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented in a 0.14 $\mu$ m SOI BCD process, the amplifier achieves 93% efficiency at 45 W output power, ${>}80\hbox{\%}$ power efficiency down to 4.5 W output power and ${>}49\hbox{\%}$ efficiency down to 0.45 W output power.
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