class-D Amplifier Research Articles

A Design Review for Biomedical Wireless Power Transfer Systems with a Three-Coil Inductive Link through a Case Study for NICU Applications

This paper outlines a design approach for biomedical wireless power transfer systems with a focus on three-coil inductive links for neonatal intensive care unit applications. The relevant literature has been explored to support the design approach, equations, simulation results, and the process of experimental analysis. The paper begins with a brief overview of various power amplifier classes, followed by an in-depth examination of the most common power amplifiers used in biomedical wireless power transfer systems. Among the traditional linear and switching amplifier classes, class-D and class-E switching amplifiers are highlighted for their enhanced efficiency and straightforward implementation in biomedical contexts. The impact of load variation on these systems is also discussed. This paper then explores the basic concepts and essential equations governing inductive links, comparing two-coil and multi-coil configurations. In the following, the paper discusses foundational coil parameters and provides theoretical and experimental analysis of both two-coil and multi-coil inductive links through step-by-step measurement techniques using lab equipment and addressing the relevant challenges. Finally, a case study for neonatal intensive care unit applications is presented, showcasing a wireless power transfer system operating at 13.56 MHz for powering a wearable device on a patient lying on a mattress. An inductive link with a transmitter coil embedded in a mattress is designed to supply power to a load at distances ranging from 4 cm to 12 cm, simulating the mattress-to-chest distance of an infant. the experimental results of a three-coil inductive link equipped with a Class-E power amplifier are reported, demonstrating power transfer efficiency ranging from 75% to 25% and power delivery to a 500 Ω-load varying from 340 mW to 25 mW over various distances.

A Reconfigurable Bidirectional Wireless Power and Full-Duplex Data Transceiver IC for Wearable Biomedical Applications.

This paper presents a reconfigurable bidirectional wireless power and data transceiver (RB-WPDT) integrated circuit (IC) for wearable biomedical applications. The proposed transceiver can be reconfigured as a differential class-D power amplifier or a full-wave rectifier depending on the mode signal to facilitate power transfer between devices. Additionally, the RBWPDT system supports full-duplex (FD) data transmission via a single inductive link, enabling real-time control and monitoring between devices. The proposed FD method utilizes frequency shift-keying pulse-width modulation (FSK-PWM) for downlink and load shift-keying (LSK) for uplink, achieving simultaneous bidirectional data transmission by ensuring that the FSK-PWM downlink and LSK uplink data channels operate independently with minimal interference. The measured downlink and uplink data rates are 250 kb/s and 67 kb/s, respectively. The measured overall DC-to-DC efficiency is 49%, while the power delivered to the load (PDL) is 120 mW at a 5 mm distance. The proposed chip is fabricated using a 180-nm BCD CMOS process.

An All-Digital Spread Spectrum Method with Distortion Correction for Filterless Digital Class-D Amplifiers

An All-Digital Spread Spectrum Method with Distortion Correction for Filterless Digital Class-D Amplifiers

A Novel Self-Oscillating T-3level Half-Bridge Inverter for Class-D Amplifiers

A Novel Self-Oscillating T-3level Half-Bridge Inverter for Class-D Amplifiers

A 121.7-dB DR and $-$109.0-dB THD$+$N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

A 121.7-dB DR and $-$109.0-dB THD$+$N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells

Nonlinear control-based class-D amplifier for audio intelligent infrastructure applications

Nonlinear control-based class-D amplifier for audio intelligent infrastructure applications

Compact RF transmission unit for nuclear quadrupole resonance spectroscopy

Nuclear quadrupole resonance (NQR) spectroscopy is a non-destructive measurement technique that enables to detect materials of interest very accurately. This technique works by sending high power electromagnetic waves with radio frequency (RF) very specific to the molecular structure to excite the sample and detecting the respond signal with the same frequency. Portable NQR detectors can be potentially developed to detect explosives with non-metallic containers in the fields. However, commercial RF high power amplifiers are large and heavy, so they are not practical for field usage. In this work, we demonstrate a compact NQR transmission part which composed of an active input signal conditioner, a class-D amplifier, and an NQR coil. The active input signal conditioner circuit will convert a single rf pulse with low amplitude (<0.5Vp) to two pulses (with 180° phase difference) and they are subsequently amplified to TTL level. In the class-D amplifier, the pre-amplified pulses are further amplified by a high voltage gate driver IC to 24V amplitude. These high voltage pulses are converted to a single 24V pulse by MOSFETs connected in a half bridge configuration. Finally, the amplified pulse is fed to the NQR coil, i.e., a low impedance LC series resonance circuit. The voltage across the coil at resonance frequency is about 1kVpp.

A 6.78-MHz Wireless Power Transfer System With Inherent Wireless Phase Shift Control Without Feedback Data Sensing Coil

This article presents a 6.78-MHz wireless power transfer (WPT) system with a differential class-D power amplifier (PA) for the transmitter (TX) and a delay-tuned rectifier for the receiver (RX). Besides the RX local voltage regulation, we propose a fully integrated TX global power regulation with wireless phase shift control without any extra off-chip components. Furthermore, the proposed system eliminates the feedback data-sensing coil used in prior arts, thus greatly improving the system integration level and reducing the circuit complexity. On the TX side, the global loop regulates the transmitted power through the duty cycle control of 1X/2X operation modes of the class-D PA to improve the system efficiency over a wide load range. On the RX side, we realize ac–dc power rectification and voltage regulation with a delay-tuned rectifier. The TX and RX chips fabricated in a standard 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m CMOS process used 3.3-V devices. Measured results show that the circuit can obtain a system efficiency improvement up to 14.2% at light load conditions, with the proposed wireless phase shift control regulating the TX global power. The peak end-to-end system efficiency is 77%, and the maximum output power is 0.9 W with a 3.3-V output voltage.

Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers

The Design of efficient, safe, and reliable circuits is a prime objective in high-voltage (HV) electronic systems, such as switched-mode power amplifiers (PAs). One of the main causes of efficiency degradation and reliability problems, in these amplifiers, is the shoot-through current from the HV power supply to the ground. To eliminate such current, a dead time generator (DTG) is used to modify the signals propagating through the high-side and low-side gate drivers by adding a fixed dead time between them. However, any delay mismatch between these gate drivers can reduce the dead time to the point that it becomes negative. In this paper, an HV-DTG architecture is introduced. The architecture mitigates the effects of delay mismatch variations in gate drivers, which can result from parameters mismatch, fabrication process variations, and temperature variations. An HV switched-mode class-D power amplifier is used to illustrate the performance of the DTG. The amplifier is implemented in a low-cost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu m$ </tex-math></inline-formula> HV CMOS process. The total area of the PA is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~mm^{2}$ </tex-math></inline-formula> , where the DTG covers an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.066~mm^{2}$ </tex-math></inline-formula> . A measured system’s efficiency of 95.14% is achieved with the shortest dead time of 10.8 ns, which is 1.38x smaller than the generated dead time in comparable state-of-the-art HV dead time generators.

Wireless Piezoelectric Motor Drive

Nanopositioners with embedded piezoelectric motors are used in a variety of industries, from microscopy to laser processing or measurement systems. A concrete example would be fine-tuning of multiple mirror or lens units in a system. After fine adjustment of a mirror or lens, its position is expected to be maintained when the system is not energized. Features such as small size, direct drive, and maintaining position with high rigidity at power off make inertia-type piezoelectric motors suitable for such “set and go”-type applications. However, wiring with dedicated control electronics for each positioner can increase system complexity. In this study, a wireless driving method for piezoelectric inertia-type motors is introduced for the first time, to the best of our knowledge. In our approach, sawtooth signals for driving a two-phase piezoelectric inertia motor are converted into two complementary pulse-width-modulated (PWM) signals at 1.0 MHz and amplified by class-D amplifier topology, in which GaN transistors are implemented. The amplified complementary PWM signals are applied to a transmitter coil. A receiver coil, which forms an LC network with the capacitances of the piezoelectric multilayer actuators, picks up the driving signals. The filtered voltage waveform by the receiver coil is converted into a modified sawtooth signal, which can operate the piezoelectric inertia-type motor wirelessly. Initial measurements revealed that even a single driving pulse can be transmitted to the receiver coil and precise movements of the slider can be obtained. Mean step sizes for single pulse drive are 140 nm in one direction and 125 nm in the reverse direction.

An Edge-Combining Frequency-Multiplying Class-D Power Amplifier

The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65nm CMOS prototype achieves output power and system efficiency of 22.3dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.

A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier

This article presents a class-D amplifier (CDA) with high dynamic range (DR). To eliminate the typically dominant noise contribution of a resistive feedback network, the input and feedback signals are chopped and applied to a capacitive feedback network. However, this leads to high-voltage (HV) transients at the input of the loop filter, which, due to timing and impedance mismatch in the chopped feedback network, could degrade linearity and even overstress low-voltage (LV) core devices. Robust processing of the HV chopped feedback signal is guaranteed with chopper timing skew correction, chopper impedance matching, and deadbanding. The prototype, implemented in a 180-nm bipolar-CMOS-DMOS (BCD) process, achieves 121.4 dB of DR, 5.9 dB higher than state-of-the-art closed-loop CDAs, and 8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}_{\mathrm {RMS}}$ </tex-math></inline-formula> output-referred noise (A-weighted). It also achieves a peak total harmonic distortion (THD) + N of −109.8 dB and a peak efficiency of 93%/88% while driving 15 W/26 W into an 8-/4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load.

An automated system for nucleic acid extraction from formalin-fixed paraffin-embedded samples using high intensity focused ultrasound technology.

Formalin-fixed paraffin-embedded (FFPE) tissue samples are routinely used in prospective and retrospective studies. It is crucial to obtain high-quality nucleic acid (NA) from FFPE samples for downstream molecular analysis, such as quantitative polymerase chain reaction (PCR), Sanger sequencing, next-generation sequencing, and microarray, in both clinical diagnosis and basic research. The current NA extraction methods from FFPE samples using chemical solvent are tedious, environmentally unfriendly, and unamenable to automation or field deployment. We present a tool for NA extraction from FFPE samples using a high-intensity focused ultrasound (HIFU) technology. A cartridge strip containing reagents for FFPE sample deparaffinization and NA extraction and purification is operated by an automation tool consisting of a HIFU module, a liquid handling robot unit, and accessories including a thermal block and magnets. The HIFU module is a single concaved piezoelectric ceramic plate driven by a current-mode class-D power amplifier. Based on the ultrasonic cavitation effects, the HIFU module provides highly concentrated energy introducing paraffin emulsification and disintegration. The high quantity and quality of NA extracted using the reported system are evaluated by PCR and compared with the quantity and quality of NA extracted using the current standard methods.

Precise Mathematical Model of PSCM Class-D Amplifiers

A mathematical analysis of four-level (three-phase) phase-shifted carrier modulation class-D amplifiers with analog feedback is proposed. The nonlinear difference equations are extracted and solved using the perturbation theorem. In this way, a closed-form function describes the low-frequency part of the output for an arbitrary input signal. The results are generalized for an arbitrary number of levels by analogy, well matched with the previous model of two-, three-, and the proposed four-level ones. The analytical results confirm that, apart from switching frequency, the multilevel class-D amplifiers converge to linear amplifiers as the number of output levels increases. An analytical equation expresses the harmonic distortion of practically interesting five-level amplifiers with bridge-tied load. The model is verified by system-level simulations and circuit-level implementation. In this way, a prototype fully differential five-level circuit is implemented on the printed circuit board to confirm the model.

A Real-Time Calibrated Adaptive-ZVS Class-D Power Amplifier for 6.78 MHz Wireless Power Transfer System

This brief presents a class-D power amplifier (PA) with an adaptive zero-voltage switching (A-ZVS) technique for 6.78 MHz resonant wireless power transfer (R-WPT) system. In R-WPT operation, the loading impedance of a PA can be varied by the process tolerance of the LC resonant components or WPT environments, such as the resonant topology, coupling coefficient, and loading condition of the receiver. In particular, the commonly used series-parallel resonant topology suffers from resonant point deviation of primary LC tank, resulting in hard switching of the PA. Consequently, efficiency degradation and electromagnetic interference can occur under multi-MHz operation. The proposed A-ZVS feedback loop calibrates the equivalent resonant capacitance in real-time to achieve ZVS by adjusting the loading impedance to be slightly inductive. The proposed PA was fully integrated except for one switched capacitor used as the tuning element and fabricated in a TSMC 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process. The measurement results demonstrated robust ZVS operation with a peak system efficiency of 52.7 % and an enhanced maximum transmitting power of 107 %.

A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of −109.1 dB and can deliver a maximum of 14 W into an 8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load with 93% efficiency while occupying a silicon area of 5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Single-Voltage-Source Class-D Boost Multi-Level Inverter with Self-Balanced Capacitors

A symmetric single-source 7-level DC-AC converter with voltage gain of 3 and self-voltage balance is presented by combining the Class-D amplifier and the diode-clamped DC-AC converter. There is only one switch is switched for any time in this circuit. As a result, the conversion efficiency can be upgraded significantly as well as the control strategy can be simplified considerably. In the paper, the operation principle and circuit design of this converter are analyzed in detail, and its feasibility and effectiveness are verified by simulation and digital control, respectively.

A −121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter Nonlinearity Suppression

Class-D audio amplifiers produce electromagnetic interference (EMI), which often needs to be suppressed by an external <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> filter. However, due to component nonlinearity, this filter can itself cause significant distortion. This article presents a class-D amplifier that suppresses <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> filter nonlinearity by 49 dB and is robust to ±30% variations in its cutoff frequency. This is achieved by a dual-loop architecture, in which an inner loop provides stability, while an outer loop provides the high gain needed to suppress the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> filter and output-stage nonlinearity. A prototype, implemented in a 180-nm BCD process, achieves −121.5-dB total harmonic distortion (THD) and −107.1-dB THD+N, which is maintained to within 3 dB even as the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> filter cutoff frequency is varied from 62 to 106 kHz. It can deliver a maximum of 21 W into a 4- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load with 87% efficiency and 12 W into an 8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load with 91% efficiency, measured at 10% THD.

An Incremental-ΔΣ ADC With 106-dB DR for Reconfigurable Class-D Audio Amplifiers

This paper presents a hybrid ADC, by combining an incremental converter with a delta-sigma modulator (ΣM) to achieve a high-dynamic response, intended for audio applications. The circuit uses a zero + first-order incremental converter with a 4-b quantizer and a third-order ΣM. Combining the two binary outputs generates a 576-kHz 6-bit binary flow for directly driving a class-D amplifier. A 4-bit flash used in the incremental running at 1/16 the clock frequency and a one-shift DEM technique compensate for the capacitive mismatch and cancel its effect for input signals lower than -35 dBFS. The proposed ADC, fabricated in a 0.18-m CMOS process, occupies an active area of 1.2 mm and consumes 7.2 mW with a 1.8-V supply. The circuit achieves an SNR/SNDR/DR of 96.8/94.45/106 dB for a 21-kHz signal bandwidth.

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.