Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers

Abstract

The Design of efficient, safe, and reliable circuits is a prime objective in high-voltage (HV) electronic systems, such as switched-mode power amplifiers (PAs). One of the main causes of efficiency degradation and reliability problems, in these amplifiers, is the shoot-through current from the HV power supply to the ground. To eliminate such current, a dead time generator (DTG) is used to modify the signals propagating through the high-side and low-side gate drivers by adding a fixed dead time between them. However, any delay mismatch between these gate drivers can reduce the dead time to the point that it becomes negative. In this paper, an HV-DTG architecture is introduced. The architecture mitigates the effects of delay mismatch variations in gate drivers, which can result from parameters mismatch, fabrication process variations, and temperature variations. An HV switched-mode class-D power amplifier is used to illustrate the performance of the DTG. The amplifier is implemented in a low-cost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu m$ </tex-math></inline-formula> HV CMOS process. The total area of the PA is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~mm^{2}$ </tex-math></inline-formula> , where the DTG covers an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.066~mm^{2}$ </tex-math></inline-formula> . A measured system’s efficiency of 95.14% is achieved with the shortest dead time of 10.8 ns, which is 1.38x smaller than the generated dead time in comparable state-of-the-art HV dead time generators.