class-D Amplifier Research Articles

A 4Ω 2.65W Class-D Audio Amplifier With Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for Adaptive Speaker Protection

In this paper a class-D smart speaker driver is presented that can deliver 2.65 W at 1% THD into a 4Ω load. Maximal output power is maintained at low battery voltage by supplying the class-D amplifier from a DC-DC boost converter. Speaker damage is avoided by a speaker protection algorithm that runs on an embedded DSP. The protection algorithm estimates the membrane excursion and voice coil temperature using a speaker model that tracks the speaker impedance which is determined by measuring the speaker current with less than 2% relative error. A sample & hold technique is presented that rejects the load current ripple by sampling at the moments where the instantaneous load current equals the average current. At full output power the combined efficiency of the class-D amplifier and DC-DC boost converter is higher than 80%. The complete system is implemented on a single chip that measures 6.6 mm2 and is fabricated in a 0.14 μm CMOS technology with a 5 V gate-oxide option.

A digital input class-D audio amplifier with sixth-order PWM

A digital input class-D audio amplifier with a sixth-order pulse-width modulation (PWM) modulator is presented. This modulator moves the PWM generator into the closed sigma—delta modulator loop. The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma—delta modulator. Therefore, at the output of the modulator, a very clean PWM signal is acquired for driving the power stage of the class-D amplifier. A sixth-order modulator is designed to balance the performance and the system clock speed. Fabricated in standard 0.18 μm CMOS technology, this class-D amplifier achieves 110 dB dynamic range, 100 dB signal-to-noise rate, and 0.0056% total harmonic distortion plus noise.

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87mm2.

A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma---delta ( $$\Upsigma\Updelta$$ Σ Δ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD ? 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.

A Class-D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-μm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 μW from a 1.2-V power supply.

PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators

This paper introduces a new Pulse-Width Modulation (PWM) control scheme for buck regulators that combines phase chopping with frequency hopping to achieve spur-free operation while delivering low output noise floor with no subharmonics due to hopping. The proposed regulator hops between two, four, or eight switching frequencies, but chops their phases to fully eliminate spurs, even with only two frequencies. Peaking in the noise floor around the eliminated spurs is minimized by hopping as fast as every switching cycle, and by spacing the frequencies 0.5 MHz apart. This results in less than 1.7% drop in the regulator's efficiency and less than 4 mV increase in the voltage ripple. Implemented in standard 0.35- μm CMOS technology, the proposed regulator's area and power overhead beyond conventional single-switching-frequency design is only 8% and 3%, respectively. With a spur-free spectrum and low noise floor across all frequencies, the proposed architecture can serve as a low-noise regulator for powering noise-sensitive loads without post linear regulation or additional passive filtering. Moreover, spur-free operation facilitates its integration in mixed-signal systems on chip without interfering with sensitive circuits that share the same substrate or power rails. The proposed architecture is also a good candidate for implementing class-D amplifiers, as it preserves the control loop's linearity.

A Novel 3D Filter-less Class-D Audio Amplifier with Stereo Enhancement

This paper presents a novel 3D filter-less class-D audio amplifier with the stereo enhancement structure. The principle of this stereo enhancement scheme has been analyzed. It shows that the amplifier with this proposed circuit has a better live effect than the traditional class-D audio amplifiers. In this amplifier, the input audio signal from one channel can be amplified in two channels at the same time by way of cross-coupling. The ratio of gains in the two channels also can be adjusted by changing the external resistance, which improves the stereo effect. A practical implementation in the SMIC CMOS 0.18-μm process has been done to validate the theoretical results. When a sine signal with 1 kHz frequency and 100 mV amplitude is applied in one channel and a DC applied signal in the other, the amplifier demonstrates a gain difference of 9.4 dB. A double-sided natural sampling PWM is used in the proposed class-D amplifier to eliminate low-pass filter. The experimental result shows that the amplifier can deliver 2.5 W × 2 into 2 Ω loads at 3.3 V power supply and the THD + N is less than 0.1% without the external filters.

Class-D Amplifier Power Stage With PWM Feedback Loop

This paper presents a second-order pulsewidth modulation (PWM) feedback loop to improve power supply rejection (PSR) of any open-loop PWM class-D amplifiers (CDAs). PSR of the audio amplifier has always been a key parameter in mobile phone applications. In contrast to class-AB amplifiers, the poor PSR performance has always been the major drawback for CDAs with a half-bridge connected power stage. The proposed PWM feedback loop is fabricated using GLOBALFOUNDRIES' 0.18-μm CMOS process technology. The measured PSR is more than 80 dB and the measured total harmonic distortion is less than 0.04% with a 1-kHz input sinusoidal test tone.

A Low-EMI 3-W Audio Class-D Amplifier Compatible With AM/FM Radio

A 3-W audio class-D amplifier compatible with AM/FM radio while requiring minimal external filtering is presented. The amplifier uses driver slew rate control to reduce electromagnetic interference (EMI) in the FM band and digital modulation to spread the PWM common-mode signal and place a null at the tuned AM channel. Two original feedback techniques are employed to linearize the H-bridge. One cancels signal-dependent propagation delays in the H-bridge to improve harmonic distortion and eliminate high-frequency noise folding into the audio band. The second technique boosts the power supply rejection ratio to simplify and reduce the cost of supply filters. The amplifier system, implemented in a standard 110-nm CMOS process, operates with a supply voltage ranging from 2.7 to 6.6 V and achieves an SNR of 95 dB and 85% efficiency.

A Three-State Signal Coding Scheme for High Efficiency Class-S Amplifiers

A three-state signal coding scheme is proposed for driving Class-S amplifiers with higher efficiency than conventional techniques. The approach is formulated in the framework of polar modulation, where the magnitude is controlled by a timing code that specifies positive and negative rectangular pulses as well as a third zero state, and the phase is varied by modulating the clock delay. In particular, high efficiency is attained when the active pulse widths are a half-cycle of the carrier frequency, and the zero-state is formed by skipping pulses. In this case, full-amplitude modulation has the same efficiency as a Class-D amplifier, and is only slightly degraded as the amplitude is decreased. In addition, the technique operates at only <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$2{\times}$</tex></formula> sampling and is very simple to implement. Spectral analysis is performed for baseband signals consisting of single tones, 2-tone suppressed-carrier, and bandlimited random noise. The latter case emulates real communication signals and is shown to exhibit good spectral characteristics and low error-vector magnitude in the time domain. An important application of this technique is in all-digital, power-efficient power amplifiers for cellular base stations and handsets.

Performance comparison of integrated fully-differential filterless class-D amplifiers with different feedback techniques

Two integrated stereo fully differential filterless class-D amplifiers are presented in this paper. The object is to develop a modulation of a class-D audio amplifier with high power efficiency in this paper. The traditional H-bridge class-D audio amplifier has a shortcoming of large signal distortion which is worse than realized. However, the proposed circuit improves the drawback and provides high power efficiency at the same time. The circuit implements a modified scheme of pulse-width modulation. In this paper, we presented two class-D amplifiers, compared their differences and explained why the efficiency and distortion performance can be modified. The increase in total harmonic distortion (THD) is due to non-linearity in the triangle wave. To overcome this problem, a negative feedback from the output of the switching power stage is adopted to reduce the THD. When a 0.7-VPP and 1 kHz sine wave is used as an input signal, the minimum THD is 0.029 % and the maximum power efficiency is 83 %. The fully differential class-D audio amplifier is implemented with a TSMC 0.35-μm 2P4M CMOS process, and the chip area is 2.57 × 2.57 mm2 (with PADs).

Self-oscillatory class-D power amplifiers with a hysteresis-free relay element

For a self-oscillatory class-D power amplifier, structural models and mathematical formulas are derived by the harmonic-balance method, in order to calculate the frequency and amplitude of self-oscillations and the mean processes occurring under the action of a slowly varying input signal. Formulas for the parameters of these models are determined. For the mean processes, the stability condition of the structural model is established. Transient processes in the amplifier are plotted in the case of constant and sinusoidal input signals, on the basis of a Matlab/Simulink model.

Multi-Turn Transmit Coil to IncreaseB1Efficiency in Current Source Amplification

A multi-turn transmit surface coil design was presented to improve B1 efficiency when used with current source amplification. Three different coil designs driven by an on-coil current-mode class-D amplifier with current envelope feedback were tested on the benchtop and through imaging in a 1.5 T scanner. Case temperature of the power field-effect transistor at the amplifier output stage was measured to evaluate heat dissipation for the different current levels and coil configurations. In addition, a lower power rated device was tested to exploit the potential gain in B1 obtained with the multi-turn coil. As shown both on the benchtop and in a 1.5 T scanner, B1 was increased by almost 3-fold without increasing heat dissipation on the power device at the amplifier's output using a multi-turn surface coil. Similar gain was obtained when connecting a lower power rated field-effect transistor to the multi-turn coil. In addition to reduce heat dissipation per B1 in the device, higher B1 per current efficiency allows the use of field-effect transistors with lower current ratings and lower port capacitances, which could improve the overall performance of the on-coil current source transmit system.

A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid

A class-D amplifier with pulse code modulated (PCM) digital input is developed for a low-power digital hearing aid. A 16-bit 40-kbps PCM digital input is noise-shaped by a third-order digital sigma-delta modulator (SDM) which provides 1.5-bit digital output. The 1.5-bit digital output of the digital SDM is converted to a three-level analog signal by a simple digital-to-analog converter (DAC) and then applied to an analog SDM. The analog SDM provides pulse density modulated (PDM) signal to drive a power switch. The PDM output is fed back to the input of the analog SDM in order to suppress the noise of the power switch. While the integrators of the analog SDM are implemented with switched-capacitor (SC) circuits for a well-defined frequency response of the modulator loop filter, the feedback path from the power switch output is realized with a continuous-time (CT) integrator for effective noise suppression. The class-D amplifier with PCM digital input has been implemented in a standard 0.13-μm CMOS process. With 160-Ω load of speaker, the maximum output power delivered to the load is 1.14-mW while the efficiency of the power switch is 97-%. The signal\mathchar702D to\mathchar702D noise+distortionnratio (SNDR) and dynamic range (DR) of the class-D amplifier are measured to be 80.6-dB and 87-dB, respectively. The class-D amplifier consumes 0.38-mW from a 1.2-V power supply including the driving power of the power switch.

Filterless Class-D Amplifier With Pseudorandomized Carrier Frequency Modulation for EMI Reduction

This paper presents a filterless Class-D amplifier with pseudorandomized carrier frequency modulation (PRCFM) to mitigate electromagnetic interference (EMI) issue associated with the removal of an off-chip LC filter. The designed filterless Class-D amplifier occupies a total area of 1 mm2 and is fabricated in 0.18-μm CMOS process technology. The proposed PRCFM circuit occupies only less than 1% of the IC area. Measurement results have demonstrated the effectiveness of the PRCFM scheme for EMI reduction. The PRCFM scheme consumes very little additional power and therefore does not affect the power efficiency of the amplifier. In addition, the proposed scheme also maintains very good total harmonic distortion over the audio band of interest (100 Hz to 6 kHz) and modulation index range.

Dynamic Power-Loss Reduction for Over-Temperature Protection of Multilevel Class-D Amplifier

 Abstract—Class-D amplifier has been a popular device because of its high power efficiency. However, its ability of high power delivery also brings about over-temperature problem caused by consuming large power-loss over a long time. This paper therefore presents a control method to dynamically reduce the total power-loss of multilevel class-D amplifier according to the value of integrated temperature sensor. The driving (static) power-loss is reduced by limiting the driving current which can be achieved by reducing the output levels of the amplifier. In addition, the switching (dynamic) power-loss is diminished by segmenting the power transistors and gate drivers and selectively enabling parts of them according to the power demand. Therefore, the total power-loss of the amplifier is well controlled and reduced in order to prevent over-heating itself. Under the protection scheme, experimental results show that the total power-loss (excessive heat) and corresponding temperature difference on package can be reduced to only 15% of maximum value which demonstrates the effectiveness of proposed scheme.

High efficiency GaN current‐mode class‐D amplifier at 2.6 GHz using pure differential transmission line filters

In class-D operation the impedances of the output network at each harmonic frequency at the intrinsic terminals of the transistors are of main importance. This reported work demonstrates a new concept using pure differential transmission line filters for the matching of these impedances. Furthermore, de-embedding techniques are used to compensate the impedance transforming characteristics of the package parasitics. A current-mode class-D (CMCD) amplifier with a power-added efficiency (PAE) of 62% and a corresponding output power of 29.5 W at 2.6 GHz has been demonstrated. To the authors' knowledge, these are the highest reported values of the PAE as well as the output power at this frequency for a CMCD.

Dynamic power efficiency improvement for PWM class-D amplifier

Dynamic power efficiency improvement for PWM class-D amplifier

Intrinsic Distortion of a Fully Differential BD-Modulated Class-D Amplifier With Analog Feedback

This paper presents a mathematical analysis of a fully differential BD-modulated Class-D amplifier with analog feedback, i.e., one having a bridge-tied-load output configuration with negative feedback and ternary PWM signal. Notwithstanding the highly nonlinear nature of the amplifier's operation, an extremely accurate closed-form expression for the audible output signal is derived and verified based on computer simulations. This expression demonstrates that there exist larger high-order intrinsic distortions (e.g., 5th-order harmonic distortion and intermodulation distortion) for BD-modulation, compared to that for AD-modulation (binary PWM signal). Furthermore, the 3rd-order harmonic distortion has a roughly parabolic response as a function of the magnitude of the input signal and reaches its peak when the modulation index of the input signal is around 0.7. Overall, the BD-modulated Class-D amplifier has a larger intrinsic distortion for small input signal but a smaller intrinsic distortion for large input signal, compared to AD-modulated designs.

A new stereo enhancement circuit for class-D amplifier

A new stereo enhancement circuit for class-D amplifier