class-C Voltage-controlled Oscillator Research Articles

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.

A 0.49 mm2 CMOS Low-Power TVCO Achieving FoM of 190.36 dBc/Hz for 5G New Radio Application

This paper describes the implementation of low-power, low-phase-noise (PN), and robust startup tailless class-C voltage-controlled oscillator (TVCO) for 5G new radio (NR) technology. It features dual gate voltage control source biasing to generate fast startup and differential signal amplitude balancing, thus eliminating the requirement of the conventional tail current source, which introduces more parasitic capacitance that affects the oscillation frequency, phase noise, and power consumption. The TVCO is fabricated in 180 nm complementary metal-oxide semiconductor (CMOS) technology, oscillating at 2.59 GHz 5G NR carrier frequency with an output voltage swing of 1.7 V and low-phase-noise of -122 dBc/Hz at 1 MHz offset with supply voltage headroom of 0.7 V. Without additional features added, the TVCO consumes very low-power and a small die area of 0.98 mW and 0.49 mm2, respectively. The achieved figure of merit (FoM) is 190.36 dBc/Hz.

A Sub-100 Fs RMSjitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference

A 20-GHz fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> analog phase-locked loop (PLL) leveraging a novel high-speed charge pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable 2.5-GHz frequency reference using Texas Instrument&#x2019;s indigenous bulk acoustic wave (BAW) resonator is demonstrated. The low noise high-frequency reference allows for significant lowering of the division modulus leading to enhanced suppression of CP, phase-frequency detector (PFD), and loop-filter (LF) noise. A low noise class-C transformer-coupled voltage-controlled oscillator (VCO) further allows for excellent jitter performance over wide integration bandwidths (BWs) while still working with a nominally low PLL loop BW. Capability is built into the design to characterize the PLL with either BAW or external reference. The design is implemented and fabricated in the GlobalFoundries 22-nm fully depleted silicon on insulator (FD-SOI) process. The class-C VCO is measured to be centered at <inline-formula> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula>19.7 GHz with 16&#x0025; tuning range (TR) while maintaining a flat <inline-formula> <tex-math notation="LaTeX">$\vert {\rm FOM}\vert \sim $ </tex-math></inline-formula>188 dBc/Hz (10-MHz offset) over the entire TR. The PLL measures an excellent jitter and <inline-formula> <tex-math notation="LaTeX">$\vert {\rm FOM}_{j}\vert $ </tex-math></inline-formula> of 65/92 fs and <inline-formula> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula>249/245 dB in integer/fractional modes, respectively.

Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process

This paper presents an integer-N phase-locked loop (PLL) for an RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback loop are proposed. The frequency range of the VCO is 4.5–6.1 GHz, the target frequency of the proposed PLL is 2.4 and 5.8 GHz in the industry–science–medical band. It is designed with a same phase margin and bandwidth using one loop filter. The proposed PLL consumes less than 8 mW from a 1.8 V power supply with a settling time of fewer than 20 μs and an area of 1200 μm × 800 μm in the 180 nm CMOS process. For a carrier frequency offset of 1 MHz, the measured phase noise is −118.5 dBc/Hz at 2.4 GHz and −116.6 dBc/Hz at 5.8 GHz. Its FoM including the phase noise is −197 dB at 2.4 GHz and −202.8 GHz at 5.8 GHz, outperforming other PLLs designed in the 180 nm CMOS process.

A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array

This brief presents a class-C voltage-controlled oscillator (VCO) that ensures a robust start-up with low phase noise and high power efficiency. The proposed start-up scheme, which uses a voltage converter that operates according to the output state, relieves the start-up difficulty by supplying a timevarying bias voltage to the core transistors and allows the VCO to operate in an optimal state. The start-up circuitry is enabled only during initial operation, so power efficiency is improved without phase noise degradation. Furthermore, a capacitor array with a high quality factor is implemented by a direct capacitor connection that exhibits low series resistance. Fabricated with a 65-nm CMOS, the VCO demonstrates a frequency tuning range of 13.1% from 19.3 to 22.0 GHz. The measured minimum phase noise at a 1-MHz offset is --106.33 dBc/Hz at an oscillation frequency of 19.7 GHz, while dissipating 3.8-mW of power from a 1.0-V supply. The VCO occupies an active area of 0.064 mm2. It reveals a figureof-merit and figure-of-merit with area of --186.4 and --198.3 dBc/Hz, respectively.

A PVT-Insensitive Optimal Phase Noise Point Tracking Bias Calibration in Class-C VCO

This paper presents a Class-C voltage-controlled oscillator (VCO) with bias voltage calibration that automatically finds the low-phase noise point and achieves robust start-up regardless of PVT variation. This VCO structure also has the bias circuit that compensates for temperature changes even when calibration is not applied. Through these techniques, the problems of robust start-up and vulnerability to PVT variation, which are chronic problems of Class-C VCO, are overcome. The proposed VCO was designed in a 28 nm CMOS process. Simulation results show that this VCO has an operating range from 3.717 to 4.675 GHz, resulting in a frequency tuning range (FTR) of 22.8%. In addition, power consumption was 2.135 mW, phase noise at 1 MHz was −124.1 dBc/Hz, and the figure of merit (FoM) was −192.2 dBc/Hz. The chip area was very small at 0.196 mm2.

A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity

This article presents a low supply voltage and low-power charge-pump phase-locked loop (CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {ref}}$ </tex-math></inline-formula> adaptive adjustment mechanism is analyzed in the class-C voltage-controlled oscillator (VCO) with dual-mixed loops, which eliminates the PN’s sensitivity to temperature and process. Moreover, based on resistance-based accurate current replication, the low-power and low-current mismatch charge-pump (CP) circuit structure is proposed to reduce the reference spur of the PLL. In addition, by using the dynamic current compensation scheme, the power consumption of the CP is greatly reduced. The proposed PLL is fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> RF CMOS process with an area of 1.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show that the proposed PLL achieves a 2.24–2.85-GHz frequency tuning range and a PN of −123.97 dBc/Hz at 1-MHz offset from a 2.55-GHz carrier. The measured reference spur is −89.4 dBc at 40-MHz offset frequency and the total power consumption is 2.62 mW at the 0.8-V power supply voltage.

A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS

This letter presents a circuit solution to extract the fourth harmonic from a class-C voltage-controlled oscillator (VCO). The tail capacitor in the class-C oscillator is replaced by a dual-resonance network that allows the extraction of the fourth harmonic, while yielding low impedance at even harmonics, which is key to maintaining transistor operation in class-C. The validity of the proposed approach is demonstrated on a 20-GHz 28-nm CMOS oscillator. The circuit achieves a phase noise as low as −111 dBc/Hz at 3-MHz offset from a 78-GHz carrier while consuming 57 mW, with a figure of merit (FoM) of −182 dBc/Hz, 12% tuning range, and a dc to RF conversion of 0.7%. The undesired harmonics are suppressed by more than 70 dB.

A 92 fs&lt;sub&gt;rms&lt;/sub&gt; jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm2. By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

Low Phase Noise and Wide-Range Class-C VCO Using Auto-Adaptive Bias Technique

This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of −105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3–10.6 mW of power. The figure-of-merit with tuning range (FoMT) of this design reached 191.1 dBc/Hz.

A Modified Darlington-Based Class-C VCO With Simultaneous Optimization of Phase Noise/FoM in GaAs Technology

This letter presents a modified Darlington-based (DB) class-C voltage-controlled oscillator (VCO) topology which achieves a cooptimization of phase noise and figure of merit (FoM) in GaAs technology. Both the Darlington pair and noise shifting techniques are introduced to improve the phase noise in class-C VCOs. Balanced and differential architectures are used to absorb the strength of both the Colpitts and class-C VCO topology with a simple trick of two cascaded stages in the VCO core, which elevates the VCO driving capability with no degradation of power efficiency. In addition, the startup conditions and capacitive feedback factors are derived and compared in both mathematical and simulation manners, which proves the superiority of the topology. The proposed VCO is fabricated in a GaAs bipolar high electron mobility transistor (BiHEMT) technology which demonstrates a frequency range of 2.76–2.91 GHz with a current consumption of 9.5 mA at 5 V supply, a phase noise of −138.6 to −135.9 dBc/Hz at 1 MHz offset from the carrier, an output power of −3.06 to −4.18 dBm, and a peak FoM of −191.2 dBc/Hz at 1 MHz offset. To the best of the authors’ expertise, the proposed DB class-C VCO achieves both exceptional phase noise and FoM, which far outweigh that of the existing GaAs.

A Low-Voltage Robust Class-C VCO With Dual Digital Feedback Loops

This brief presents a low-supply-voltage robust class-C voltage-controlled oscillator (VCO) with the dual digital feedback loops. One is the digital adaptive bias loop (DABL) which is proposed to ensure startup robustness and improve the phase noise performance of the VCO. And the other is the digital amplitude control loop (DACL), which is adopted to stabilize the oscillation amplitude over process, voltage and temperature (PVT) variations. Moreover, a cooperative algorithm is also proposed in order to make the dual digital loops work properly. Besides, the offset canceling comparators are adopted to guarantee the stability of the digital loops. The proposed VCO is implemented in SMIC 0.18 $\mu \text{m}$ CMOS process, achieving a phase noise of −123.3 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier and a 2.2-2.7 GHz frequency tuning range. The figure-of-merit (FoM) is −190.4 dBc/Hz with the total power consumption less than 1.28 mW at the 0.8 V supply voltage.

A 12-GHz Wideband Fractional-N PLL With Robust VCO in 65-nm CMOS

This letter presents a 12-GHz wideband fractional-N phase-locked loop (PLL) with a robust voltage-controlled oscillator (VCO). The proposed PLL uses a class-C VCO with an amplitude-adjustment circuit (AAC) to increase current during the startup process and stabilize the VCO amplitude. In order to make the circuit more compact, the control logic in the VCO is simplified. A prototype of the PLL implemented in 65-nm CMOS, with an active area of 1.5 mm2, can achieve −106 dBc/Hz phase noise (PN) at 1-MHz offset from a 11.96-GHz carrier. It draws 18.2-mW power with 48-MHz reference frequency from a 1.2-V supply.

A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving – 120 dBc/Hz Phase Noise at 1 MHz Offset

The performance of low-powered transceivers is required to meet stringent specifications for an advanced wireless radio application. It is critical for a voltage-controlled oscillator (VCO) to meet multi-standard and multiple frequency operation with low-power consumption and amplitude enhanced complementary mode of operation. This paper proposes a novel technique for wide tuning range in a complementary class-C VCO employing a capacitive-source degeneration (CSD) to meet multi-standard operation for low-power transceivers. The technique that employs two sets of symmetrical split PMOS biased current source operating in the subthreshold region achieves the desired low phase noise (PN) performance at a tuning range of 2.2-2.9 GHz with a supply headroom of 1.2 V. The control of the dc bias point reduces the conduction angle, which improves the current efficiency, power consumption, and PN. Concurrently, an auxiliary -g m NMOS only class-B oscillator is incorporated to mitigate the start-up issue of the class-C VCO. At the center frequency of 2.45 GHz, the proposed VCO achieves a power consumption of 1.73 mW, phase noise of -120 dBc/Hz at the 1-MHz offset, and a figure-of-merit (FoM) of 185.41 dBc/Hz at 1 MHz. The total active chip area is only 0.3-mm 2 excluding bond pads. The proposed VCO serves as a promising solution for low-power wireless communication systems.

Phase Noise Analysis of Bipolar Class-C VCOs With Delay in Oscillator Loop

The expression for phase noise of a bipolar class-C voltage controlled oscillator (VCO) with an ideal delay in the oscillator loop is derived in this paper. The impact of internal device parasitics is then quantified and supported with circuit simulation results. A bipolar class-C VCO is fabricated in a 130-nm BiCMOS technology to validate the analytical predictions. It exhibits a phase noise performance of −112.2 dBc/Hz at 1-MHz offset when running at 19.2 GHz. The tuning range is 7%, and the overall FoM and FoMT are 180.4 dBc/Hz and 177.3 dBc/Hz, respectively.

A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control

A 400[Formula: see text][Formula: see text]W near-threshold supply class-C voltage controlled oscillator (VCO) with amplitude feedback loop and auto amplitude control (AAC) is proposed in this paper. The amplitude feedback loop and AAC ensure the robust startup of the proposed VCO and automatically adapts it to the class-C mode in steady state. Consequently, ultra-low power can be achieved in AAC mode and low phase noise, high swing can be achieved in AAC off mode. The proposed VCO with AAC gets ultra-low power consumption by limiting the oscillating amplitude and driving the proposed VCO into the deep Class-C mode. Additionally, the peak value detector is employed in this work to boost the controlling voltage of capacitors bank. Thus, a low on resistance of switch transistors is obtained, which increases the Q value of capacitors bank. The simulated phase noise is [Formula: see text]124.5[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset with the 1.16[Formula: see text]GHz oscillation frequency. In this case, the figure-of-merit including tuning range (FOMT) of proposed VCO is [Formula: see text]195[Formula: see text]dBc/Hz. The proposed VCO is fabricated in SMIC 40[Formula: see text]nm CMOS process and consumes 0.62[Formula: see text]mA from 0.65[Formula: see text]V supply. The measured phase noise is [Formula: see text]109[Formula: see text]dBc/Hz and FOMT is [Formula: see text]179[Formula: see text]dBc/Hz.

A Low-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS

A fully integrated 750~960 MHz wireless transceiver (TRX) is presented for single-tone NB-IoT applications. Effective design methodologies and techniques, from the system level to circuit level, are proposed to address various design challenges while achieving low-power consumption. The TRX consists of a low-IF receiver with 180-kHz signal bandwidth, a digital polar transmitter with 3.75-kHz signal bandwidth, and a fractional-N frequency synthesizer. Passive current mixer is employed in the receiver to improve the linearity and avoid the sensitivity degradation due to 1/ ${f}$ noise. Automatic I/Q imbalance calibration is integrated to improve image rejection ratio (IRR) with the aid of external FPGA. The transmitter is implemented in the digital polar architecture to improve the narrow-band spectrum purity, integrated with an inverse Class-D digital power amplifier (DPA) to achieve high output power and efficiency. A Class-C voltage-controlled oscillator with automatic frequency control assisted the dynamic gate biasing technique is used in the fractional-N PLL frequency synthesizer. Two prototypes are implemented in 180-nm CMOS. By optimizing analog baseband configuration in the receiver and utilizing the revised thermometer-coding and binary-coding-based array placement in the DPA, the receiver achieves 4.0-dB noise figure, 48-dB IRR, and 60-dB PGA dynamic range, and the DPA outputs 23.2dBm maximum saturation power with 44.5% PAE. Furthermore, the transmitter system verifications demonstrate 3.87% error-vector magnitude (EVM) for 891 MHz $\pi $ /4-DQPSK signals at 18.87-dBm output power with −40-dBc out-of-band rejection. The transmitter achieves a dynamic range from −35 to 20 dBm when the demodulation EVM threshold of the system is set to 10%.

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) asa building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1V, the proposed VCO consumes 0.44–1.1mW corresponding to the oscillation frequency of 1.1–1.8GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.

A 6.6 mW 1.25–2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO

A wide tuning range low phase noise phase-locked loop (PLL) frequency synthesizer based on Class-C voltage-controlled oscillator (VCO) for IEEE 802.11ah is presented. Feedback loop technique is adopted to provide dynamic gate bias to the core transistors of the Class-C VCO, guaranteeing robust start-up against process, voltage and temperature (PVT) variations. Automatic frequency control (AFC) algorithm with tail bias switching scheme is proposed to guarantee start-up condition and maintain optimum oscillation amplitude across the whole tuning range, avoiding the deterioration of figure-of-merit (FoM). Implemented in 65-nm CMOS, the presented frequency synthesizer prototype achieves a tuning range of 57%, from 1.25GHz to 2.25GHz. Drawing 5.5mA current from a 1.2-V power supply, the prototype demonstrates −127.8 dBc/Hz phase noise at 1-MHz offset and −94.6 dBc/Hz in-band phase noise from a carrier of 1.536GHz. With the proposed dynamic gate bias technique and AFC-assisted tail bias switching scheme, the wide tuning range Class-C VCO exhibits a peak FoM of 187.5 dBc/Hz, with only 2.5dB variation across the whole tuning range.

Low‐phase noise Class‐C VCO with dynamic body bias

A 2.5 GHz Class-C voltage-controlled oscillator (VCO) with dynamic back-gate-biased MOSFET is proposed. A dynamic gate biasing circuit is used to reduce power consumption by switching N-type MOS from initial Class-AB to Class-C operation in steady state. Moreover, the VCO uses dynamic back-gate bias to reduce threshold voltage of switching MOSFET during the start-up oscillation. The Class-C differential VCO is implemented in TSMC 0.18 μm bipolar-complementary-metal-oxide-semiconductor (BiCMOS) process. The measured phase noise is -124.8 dBc/Hz at 1 MHz offset frequency from 2.48 GHz carrier while consuming 2.64 mW power from a 0.8 V supply. Tuning range of VCO is 0.72 GHz, from 2.48 to 3.3 GHz, whereas the control voltage was tuned from 0 to 2 V. The VCO occupies a chip area of 446 × 840 μm 2 and provides a figure of merit of -197.55 dBc/Hz.