Abstract

The performance of low-powered transceivers is required to meet stringent specifications for an advanced wireless radio application. It is critical for a voltage-controlled oscillator (VCO) to meet multi-standard and multiple frequency operation with low-power consumption and amplitude enhanced complementary mode of operation. This paper proposes a novel technique for wide tuning range in a complementary class-C VCO employing a capacitive-source degeneration (CSD) to meet multi-standard operation for low-power transceivers. The technique that employs two sets of symmetrical split PMOS biased current source operating in the subthreshold region achieves the desired low phase noise (PN) performance at a tuning range of 2.2-2.9 GHz with a supply headroom of 1.2 V. The control of the dc bias point reduces the conduction angle, which improves the current efficiency, power consumption, and PN. Concurrently, an auxiliary -g m NMOS only class-B oscillator is incorporated to mitigate the start-up issue of the class-C VCO. At the center frequency of 2.45 GHz, the proposed VCO achieves a power consumption of 1.73 mW, phase noise of -120 dBc/Hz at the 1-MHz offset, and a figure-of-merit (FoM) of 185.41 dBc/Hz at 1 MHz. The total active chip area is only 0.3-mm 2 excluding bond pads. The proposed VCO serves as a promising solution for low-power wireless communication systems.

Highlights

  • The relentless development of ubiquitous wireless connectivity motivates the development of low-power voltage controlled oscillators (VCOs) with low phase noise (PN) performance to support complex data modulation

  • Class-C VCOs inherently suffers from a trade-off in start-up and maximum oscillation amplitude with respect to PN

  • The PN and power efficiency of class-B VCOs decreases when the ideal current source is replaced with a single transistor

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Summary

INTRODUCTION

The relentless development of ubiquitous wireless connectivity motivates the development of low-power voltage controlled oscillators (VCOs) with low phase noise (PN) performance to support complex data (de) modulation. By further splitting the tail current source transistors to an equal half, forms a lower amplitude of the common mode voltages, VCM1 and VCM2 compared to the conventional architecture, benefiting from Cs. To sustain the VCO in class-C operation mode, the output voltage amplitude of the tank in the boundary condition of saturation and subthreshold [30] are expressed as in (14) and (15), respectively. C. LOW NOISE AND LOW POWER CONTRIBUTION IN SUBTHRESHOLD CONDUCTION Fig. 6 shows the low-power complementary class-C circuit operating under subthreshold region adopting PMOS transistors as the MOS current source. The dc bias point, VBIAS,T favor towards the subthreshold biasing condition, VGS ≈ VBIAS,T ≤ Vth improving the current efficiency simultaneously with an adequate active subthreshold MOS negative conductance, gsub of the complementary class-C VCO, expressed as gsub. Gsub of a class-C VCO in subthreshold region is computed from the subthreshold drain current, IDS and is exponentially related to the gate voltage (VG), source voltage (VS ) and drain voltage (VD) of the NMOS transistor, M5 and M6 expressed as VG

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CONCLUSION
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