Class AB CMOS Research Articles

A new low voltage low power fully differential CMOS class AB current output stage with unique current drive capability

ABSTRACT This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in F T , I outmax , (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications.

Review of Efficiency CMOS Class AB Power Amplifier Topology in Gigahertz Frequencies

This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.

Low quiescent current capacitor-less LDO regulator with high slew rate super class AB CMOS OTA

This paper presents a low quiescent current capacitor-less low-dropout regulator (LDO) with high slew rate super class AB CMOS operational transconductance amplifier (OTA). The OTA of this design is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth (GBW) product and slew rate (SR). LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. The design also uses dynamic charging transistor (DCT) to enhance the transient characteristics of the circuit. The presented LDO is fabricated in a 0.18 um standard CMOS process. The circuit consumes a quiescent current of 10 uA at no load, regulating the output at 1.0V with maximum output current of 100mA from a voltage supply of 1.2V. It achieves full range stability from 1mA to 100mA load current at a maximum 100pF load capacitor.

A 1-mW Class-AB Amplifier With −101 dB THD+N for High-Fidelity 16 $\Omega$ Headphones in 65-nm CMOS

A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves −101.4-dB total harmonic distortion plus noise (THD+N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a $16\Omega \|0.33$ -nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 $\times $ improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power $\times $ THD+N[%])). It occupies 0.16 mm 2 in a standard 65-nm CMOS.

Reduced-Complexity Polynomials with Memory Applied to the Linearization of Power Amplifiers with Real-Time Discrete Gain Control

In reconfigurable power amplifiers (PAs), the efficiency can be improved by dynamically switching the discrete gain mode according to the input envelope amplitude. Nevertheless, discontinuities that occur between gain mode changes critically compromise the linearization capability of traditional digital baseband predistorters (DPDs) based on continuous polynomials with memory. To circumvent such drawback, this work introduces a model based on polynomials bounded at both sides and able to take into account commutation delays. Besides, two novel approaches are presented to the model order reduction without basis change. The effectiveness of the proposed approaches to linearize a 130 nm CMOS class AB PA commutating in real time among three gain modes is certified based on Cadence Virtuoso and Matlab simulations. The proposed memory polynomial-based model was able to accurately model both direct and inverse transfer characteristics of a three gain mode PA, showing normalized mean square error results of about − 41 dB. Besides, a 25.5 dB reduction in adjacent channel power ratio is provided by the inclusion of a 10 parameters DPD that adopts the proposed approaches, in comparison with unlinearized PA of same output mean power.

An Ultra-Low-Voltage Bulk-Driven Analog Voltage Buffer with Rail-to-Rail Input/Output Range

This paper presents a low-voltage high driving capability rail-to-rail Class-AB CMOS bulk-driven (BD) operational transconductance amplifier (OTA) for analog voltage buffer with minimal current consumption. The proposed OTA design consists of adaptively biased Class-AB differential input stage to improve the effective transconductance and adaptive load relying on nonlinear current mirrors, configured in partial positive feedback mode to enhance the overall gain. In addition, because of adaptive bias and load configuration, the load-driving capability of OTA increases for a large change in differential input. The circuit is designed using UMC 65-nm CMOS process node and is operated at supply voltage of 0.5 V with a standby current consumption of 4.25 $$\upmu $$μA. Simulation results show that the buffer based on the proposed BD-OTA achieves an average slew rate of 93.2 mV/$$\upmu $$μs for a capacitive load of 100 pF, which is nearly 29 times that of conventional OTA with 13$$\%$$% increment in quiescent power dissipation.

A 3μW Low-Power CMOS Class-AB Bilateral Current Mirror for Low-Voltage Applications

This paper presents a compact low-power bidirectional current mirror suitable for low-voltage applications. The key element is the use of a CMOS complementary input stage working in subthreshold regime; which allows setting a reduced bias current through the mirror. The circuit was simulated using LTSpice and presents class AB operation with a THD of 1% at 1MHz. The power consumption is close to 3μW as shown by simulations and experimental data from a fabricated prototype using 0.5µm CMOS technology.

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18μm CMOS technology, exhibits 86dB open loop gain and 97dB CMRR. Experimental measurements prove its correct functionality operating with 1.2V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5MHz unity gain frequency and a 3.15V/μs slew-rate for a capacitive load of 100pF, with a power consumption of 99μW.

Highly linear micropower class AB current mirrors using Quasi-Floating Gate transistors

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23dB with respect to the use of conventional biasing. A THD value better than −35dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5µm CMOS technology, are able to operate with a supply voltage of 1.2V and a quiescent power consumption of only 36µW, using a silicon area <0.025mm2.

Class-AB CMOS Buffer with Low Power and Low Leakage Using Transistor Gating Technique

A rail-to-rail class-AB CMOS buffer amplifier is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.05%), low leakage and reduced area (2.8%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with Cadence software. This analog circuit is performed with reduced performance degradation as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay range i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by 30% (in ns) at 3V square wave input. The measured quiescent current is 56μA.

A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate

A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate

A [formula omitted] class-AB CMOS differential flipped voltage follower with output driving capability up to 100 pF

A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5μm CMOS technology and the Pelgrom's mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology.

Design of micropower class AB transconductors: A systematic approach

A systematic design approach to achieve micropower class AB CMOS transconductors is presented. It includes techniques to get rail-to-rail operation and continuous transconductance tuning, based on floating and Quasi-Floating Gate transistors. Application of the proposed design approach leads to a new family of high-performance power-efficient class AB CMOS transconductors. To illustrate the feasibility of this approach, 12 transconductors derived from this common framework have been designed and fabricated in a 0.5μm CMOS technology. Measurement results show THD values for 2V inputs of −56dB for a static power of 300μW and silicon area <0.07mm2.

Low-voltage highly-linear class AB current mirror with dynamic cascode biasing

A class AB CMOS current mirror with dynamic cascode biasing is presented. Measurement results show a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. The proposed current mirror, fabricated in a 0.5 µm CMOS technology, is able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW.

High-performance micropower class AB current mirror

A novel high-performance low-power CMOS class AB current mirror is presented. The circuit combines very high linearity, very low input and high output resistance, high current handling capability and low standby power consumption. Measurement results show a THD&lt;−85 dB for input current amplitudes five times larger than the bias current.

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18μm CMOS technology parameters. Under supply voltage of ±0.7V and bias current of 5μA, it can deliver output currents as high as 14mA with THD better than −53dB and extremely high output impedance of 320MΩ while consuming only 29μW. This makes the proposed COS to have ultra large current drive ratio (Ioutmax/Ibias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9V, it can deliver extremely large output current of ±24mA corresponding to 3200 current drive ratio while consuming only 42.9μW and exhibiting high output impedance of 350MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than −45dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR−) of 125dB and 130dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.

A new CMOS current controlled oscillator with minimum phase noise based on a low parasitic resistance CCII

In this paper we present a design of a minimum phase noise current controlled oscillator in CMOS technology. Owing to their high degree of controllability, the second generation current conveyer is used as a basic block for our oscillator. Thus, the first step in our design was to improve static and dynamic behaviour of second generation current conveyers. We present therefore a design of CMOS class AB second generation current conveyors. The translinear implementation in CMOS technology was first studied and then a considerable improvement of the parasitic series resistance on port X is done by presenting a structure of CCII. With a control current of 300 µA, a reduction of RX by a factor of 10 is observed leading to a notable improvement of the frequency behaviour. This improved CCII version was used as a basic building block in the design of a new current controlled oscillator covering [100MHz-600MHz] frequency is presented. Phase noise characteristics of the presented oscillator are investigated. We present then a new methodology of modelling and optimisation of phase noise of current controlled oscillators for CMOS process. This optimization strategy leads to a minimum phase noise acting on device geometries and design sources. PSpice simulation results are performed using CMOS 0.35 µm process of AMS.

Low Voltage High Gain Linear Class AB CMOS OTA with DC Level Input Stage

Low Voltage High Gain Linear Class AB CMOS OTA with DC Level Input Stage

Electronically tunable CMOS class-AB output stage

A new technique for CMOS class-AB output stages is introduced in this Letter. The technique uses a master---slave configuration of a complementary common-source output stage. It offers the advantage that the quiescent and minimum currents of the output stage can be independently tuned. The effectiveness of the proposed technique was verified by simulations using a standard n-well 0.18 μm CMOS process with 1 V supply voltage. A voltage buffer, that includes the proposed output stage, is able to drive a capacitive load of 0.5 nF obtaining ?63 dB total harmonic distortion. The topology features also power efficiency of about 63% for a pure resistive output load equal to 50 ?.