A new CMOS current controlled oscillator with minimum phase noise based on a low parasitic resistance CCII

Abstract

In this paper we present a design of a minimum phase noise current controlled oscillator in CMOS technology. Owing to their high degree of controllability, the second generation current conveyer is used as a basic block for our oscillator. Thus, the first step in our design was to improve static and dynamic behaviour of second generation current conveyers. We present therefore a design of CMOS class AB second generation current conveyors. The translinear implementation in CMOS technology was first studied and then a considerable improvement of the parasitic series resistance on port X is done by presenting a structure of CCII. With a control current of 300 µA, a reduction of RX by a factor of 10 is observed leading to a notable improvement of the frequency behaviour. This improved CCII version was used as a basic building block in the design of a new current controlled oscillator covering [100MHz-600MHz] frequency is presented. Phase noise characteristics of the presented oscillator are investigated. We present then a new methodology of modelling and optimisation of phase noise of current controlled oscillators for CMOS process. This optimization strategy leads to a minimum phase noise acting on device geometries and design sources. PSpice simulation results are performed using CMOS 0.35 µm process of AMS.