Reducing phase noise by proper sizing of MOSFETs in LC tuned VCOs

Abstract

This work identifies the relationships between the sizes of the oscillator's core MOSFETs and the phase noise in the 1/f/sup 2/ region. Three packaged 1 GHz VCOs with the same LC tank circuit, but different gate lengths were designed and fabricated in a standard digital 0.6 /spl mu/m CMOS technology. The minimum gate length (L/sub min/) of the core MOSFETs does not result in the minimum phase noise. Instead, the minimum phase noise occurs when the gate length is L/sub opt/, and L/sub opt/ = /spl eta/ /spl middot/ L/sub min/ where /spl eta/ is a parameter that depends upon fabrication process and bias current. From measured results, the phase noise can be further decreased by 2 dBc/Hz at 600 kHz offset from 1 GHz center frequency by using the optimal sizes of the core MOSFETs.