Class AB CMOS Research Articles

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 μm design supplied at 3.3 V show very low resistance at node X (< 50 Ω), high frequency operation (∼100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/μs.

Current mode approach: High performance 0.35 μm CMOS class AB push-pull current amplifier

A very high bandwidth class AB (Push-Pull) current amplifier using the compensation resistor technique is presented and analyzed. Such technique stands as a powerful method of bandwidth enhancement for general circuits using CMOS current mirrors. The proposed bandwidth is enhanced from 675 MHz for the uncompensated current amplifier to 745MHz for the compensated one without affecting the current gain and other design parameters such as power consumption and output swing. The circuit exhibits a current gain of 20 dB and consumes 1.48 mW for ?2.5V power supply voltage. All simulation results were performed using Hspice tool with 0.35^m CMOS TSMC parameters.

Input/Output Rail-to-Rail CMOS Operational Amplifier with Shaped Common-Mode Response

This paper presents an input/output rail-to-rail class-AB CMOS operational amplifier with reduced variations in unity-gain frequency over the entire voltage range. The rail-to-rail amplifier input stage is based on two parallel-connected complementary differential pairs. Variations in the small-signal response are kept to a minimum by realizing an adequate shaping of the CM response of the input stage, while still reducing deviations in the total limiting current of the two input pairs with respect to traditional solutions. This is achieved independently of the gm-ID characteristic of the amplifier input devices and of any strict matching condition between the complementary input pairs. Experimental results from a 3-V 0.8-μm CMOS test-chip are given.

1.5V 70dB 100MHz CMOS Class-AB 상보형 연산증폭기의 설계

A 1.5V 70㏈ 100MHz CMOS class-AB complementary operational amplifier is presented. For obtaining the high gain and the high unity gain frequency, the input stage of the amplifier is designed with rail-to-rail complementary differential pairs which are symmetrically parallel-connected with the NMOS and the PMOS differential input pairs, and the output stage is designed to the rail-to-rail class-AB output stage including the elementary shunt stage technique. With this design technique for output stage, the load dependence of the overall open loop gain is improved and the push-pull class-AB current control can be implemented in a simple way. The designed operational amplifier operates perfectly on the complementary mode with 180<TEX>$^{\circ}$</TEX> phase conversion for 1.5V supply voltage, and shows the push-pull class-AB operation. In addition, the amplifier shows the DC open loop gain of 70.4 ㏈ and the unity gain frequency of 102 MHz for <TEX>$C_{L=10㎊∥}$</TEX> <TEX>$R_{L=1㏁}$</TEX> Parallel loads. When the resistive load <TEX>$R_{L}$</TEX> is varied from 1 ㏁ to 1 ㏀, the DC open loop gain of the amplifier decreases by only 2.2 ㏈.a$</TEX>, the DC open loop gain of the amplifier decreases by only 2.2 dB.

A CMOS fully balanced four-terminal floating nullor

This paper presents design and implementation of a CMOS fully balanced realization of the four-terminal floating nullor (FTFN). The proposed fully balanced FTFN (FBFTFN) is an essential building block for implementing fully balanced architectures of both voltage and current-mode analog CMOS integrated circuits (ICs). A low-power class AB CMOS realization of the proposed circuit is fabricated in a 1.2-/spl mu/m technology. The proposed circuit has numerous applications. Several applications including fully balanced amplifiers, filters, and sinusoidal oscillators are presented. All proposed design techniques and circuits are experimentally verified.

Compact low power high slew rate CMOS buffer for large capacitive loads

A new compact CMOS class AB buffer for capacitive loads is presented. Its simple implementation relies on the use of the flipped voltage follower. Simulation results from a 0.35 µm CMOS technology are presented that prove the operating principle under low power conditions. This buffer can also find application in testing of analogue CMOS VLSI circuits, as the input capacitance can be very low without diminishing its output drive capability.

A CMOS fully balanced differential difference amplifier and its applications

We present the fully balanced version of the differential difference amplifier (DDA) as an essential building block for implementing fully differential architectures of analog CMOS integrated circuits (ICs). It is demonstrated that the fully balanced differential difference amplifier (FBDDA) provides the solution for systematically developing fully differential versions of any single-ended op-amp based circuit. It is also shown that, unlike the DDA, the FBDDA exhibits a wide input range without demanding complex circuitry. A low-power class AB CMOS realization of the proposed circuit has been designed and fabricated in a 1.2 /spl mu/m technology. All proposed design techniques and circuits were experimentally verified.

A low voltage, rail-to-rail, class AB CMOS amplifier with high drive and low output impedance characteristics

This paper describes a CMOS rail-to-rail class AB operational amplifier designed to have extremely low output impedance and large current-drive capability. The amplifier uses an innovative output stage, having both source follower and common source stages working simultaneously throughout the output common-mode range. The source follower ensures low output impedance, which enables it to drive relatively large load capacitors, while the common-source gain stage provides high current drive. Furthermore, the circuit is fully functional with supplies as low as 1.5 V. The amplifier is capable of driving a maximum output current of /spl plusmn/7 mA with only 140 /spl mu/A of total quiescent current, making it power efficient, and thus appropriate for low voltage battery-powered applications.

A New CMOS Buffer Amplifier Design Used in Low Voltage MEMSInterface Circuits

To achieve low voltage high driving capability with quiescent current control, a class-AB CMOS buffer amplifier using improved quasi-complementary output stage and error amplifiers with adaptive loads is developed. Improved quasi-complementary output stage enables it more suitable for low voltage applications, while adaptive load in error amplifier is used to increase the driving capability and reduce the sensitivity of the quiescent current to fabrication process variation. The circuit has been fabricated in 0.8 μm CMOS process. With 300 O load in a ±1.5 V supply, its output swing is 2.42 V. The mean value of quiescent current for eight samples is 204 μA, with the worst deviation of 17%.

Low-voltage dynamic biasing techniquefor CMOS class AB current-mode circuits

A novel dynamic biasing technique that can be used for the design of CMOS class AB current-mode circuits is presented. The approach takes advantage of the switched capacitor (SC) technique and enables extremely low voltage operations. An application of the proposed technique to the design of a basic input stage is given and simulations showing good agreement with the expected results are provided.

Dynamic biasing for true low-voltage CMOS class AB current-mode circuits

This paper presents a dynamic biasing approach for continuous-time CMOS class AB current-mode circuits. The method allows low voltage circuits to be implemented whose supply requirements are restricted to one threshold voltage plus two saturation voltages. Fundamental limitations of the approach are analyzed and found to be compatible with a wide spectrum of analog applications, some of which are briefly discussed. A complementary current mirror, a current comparator, and a current amplifier were designed using the proposed technique. SPICE simulations using a 0.8-/spl mu/m process are provided, which confirm the overall performance of these circuits especially in terms of low-voltage capability and speed without compromising linearity.

Very low-voltage class AB CMOS andbipolar precision current rectifiers

Simple class-AB CMOS and bipolar precision rectifier circuits that operate from a single supply close to a transistor's threshold voltage are introduced. These circuits have output voltage swings comparable to the supply voltage. Results from simulations of MOS and bipolar precision rectifiers at 20 and 100 MHz, respectively, are presented. Experimental results of a test chip are presented that verify the proposed circuits. A full wave precision rectifier based on the proposed rectifier cells is discussed.

CMOS low noise class AB buffer

A novel CMOS class AB buffer circuit realisation is presented. The proposed circuit retains a simple realisation and provides low power class AB operation. It is shown that the class AB circuitry does not contribute to the noise performance of the circuit. Experimental results from a 1.2 /spl mu/m chip for the buffer and filter circuits are presented.

A 75 μW rail-to-rail class AB CMOS operational amplifier

A new class AB CMOS operational amplifier featuring rail-to-rail output swing is presented. The proposed circuit operates with an output voltage supply of 1 V only, while the overall power consumption is lower than 75 μW. The output stage shows a quiescent current of 15 μA, while it guarantees a peak current of 220 μA. The slew rate is 1.5 V μs −1 ( C 1 = 150 pF) and the THD is −63 dB, when a 0.98 V pp−10.4 kHz sinewave is applied, as measured on an experimental prototype realised with a standard 0.8 μm CMOS process. The circuit presented is suitable for use in portable hand-set systems or in medical aids.

Harmonic distortion on class AB CMOS current output stages

Linearity performance in class AB CMOS current output stages is discussed, and simplified equations are derived for the harmonic distortion. It was found that channel-length modulation and transistor mismatches are the main sources of distortion in current output stages. A novel high-performance class AB current output stage is also presented which is based on active-gain enhanced cascoded mirrors. It overcomes the nonlinearity caused by channel-length modulation and provides a very high output resistance. The linearity performance of the proposed circuit is only limited by the fundamental constraints due to transistor mismatches.

A class AB CMOS fully balanced signal generator

Mixed-signal ICs benefit greatly from processing fully balanced signals. Real-world signals are single-ended and must be converted on-chip to fully balanced signals. This article discusses a simple, accurate, low power CMOS solution to generating fully balanced signals on-chip. The design does not require common-mode feedback and provides a pin for controlling the common-mode level.

Current Mode Circuit Implementations of PWL Functions

Current-mode techniques have been used to realize improved basic building blocks of elementary piecewise linear (PWL) functions. These alternative circuit implementations, used for synthesis of precision PWL transfer characteristics, are described and compared in performance. In this paper, two optional topologies of the PWL function building blocks are proposed, based on the regulated cascode current mirror, current sources, Schottky “prebiased” diodes, and improved CMOS class AB “prebiased diodes.” The comparison of DC and high frequency performances is based on HSPICE simulation results and shows very good DC accuracy and transient time response of the proposed building blocks.

Four-quadrant class AB CMOS current multiplier

A four-quadrant class AB CMOS current-multiplier is presented. Wide input range, high dynamic range, high cutoff frequency, good linearity and low consumption are the features of the presented technique. A nonlinearity error of 1.1 % with a small-signal bandwidth of 66 MHz for a quiescent current of 25 µA and a supply voltage of 3.3 V in a 0.5 µm technology are obtained.

Current-mode class AB design using floating voltage-source

A basis for class AB operation of current-mode CMOS circuits is presented. This has led to a new CMOS class AB current conveyor suitable for VLSI implementation. The CCII has a low input resistance with a variation of only 10% over the whole linear range.