Class AB Amplifier Research Articles

A 134 GHz <formula formulatype="inline"><tex Notation="TeX">${+}4$</tex> </formula> dBm Frequency Doubler at <formula formulatype="inline"> <tex Notation="TeX">$f_{\max}$</tex></formula> in 130 nm CMOS

A +4 dBm 134 GHz frequency doubler operating at the maximum oscillation frequency (fmax) of the technology is shown in an IBM 130 nm CMOS process. The doubler is implemented in a balanced topology, driven by a chain of stacked Class-AB amplifiers, and generates the highest reported power in 130 nm CMOS beyond 100 GHz. A theoretical study of frequency doublers is presented including scaling trends across frequency and CMOS technology nodes.

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

Class-D Amplifier Power Stage With PWM Feedback Loop

This paper presents a second-order pulsewidth modulation (PWM) feedback loop to improve power supply rejection (PSR) of any open-loop PWM class-D amplifiers (CDAs). PSR of the audio amplifier has always been a key parameter in mobile phone applications. In contrast to class-AB amplifiers, the poor PSR performance has always been the major drawback for CDAs with a half-bridge connected power stage. The proposed PWM feedback loop is fabricated using GLOBALFOUNDRIES' 0.18-μm CMOS process technology. The measured PSR is more than 80 dB and the measured total harmonic distortion is less than 0.04% with a 1-kHz input sinusoidal test tone.

A Power-Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using 0.18-μm CMOS technology.

A Power-Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 µW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using 0.18-µm CMOS technology.

Analytical method for deriving consistent large–small‐signal field‐effect transistor model

AbstractThis article presents a detailed analytical method for deriving consistent large–small‐signal field‐effect transistor (FET) model. This resulted in a set of closed‐form equations relating the large‐signal model parameters to the small‐signal model ones. An improved equivalent circuit is proposed for modeling the transistor under large‐signal operation. In this circuit, RF nonlinear current sources are used to model the distributed effect of the gate–source and gate–drain junctions. The dispersion between DC and RF drain current characteristics is modeled using an improved back‐gating technique. The predictive model capabilities are illustrated with measured and simulated S‐parameters, output power at fundamental and harmonics frequencies of a commercial packaged GaAs FET device. The model is then fully validated by comparing measured and simulated results of output power, efficiency, and intermodulation distortion of a class AB amplifier designed at 1.9 GHz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1001–1008, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27495

Distortion Modeling of Class-AB Opamp with Nonlinear Coefficients Derived by Least Square Method

The distortion of class-AB operational amplifier is modeled in this paper. The signal path of the class-AB amplifier is approximated by two third-order polynomials with different coefficients. These coefficients can be obtained by exploring the DC characteristics. With the help of Fourier transform, the analytical expressions of harmonic components and distortion factors are derived also. The agreement between simulated results and theoretical analyses validated the modeling in this paper.

A High-PSRR Reconfigurable Class-AB/D Audio Amplifier Driving a Hands-Free/Receiver 2-in-1 Loudspeaker

A high-power-supply-rejection-ratio (PSRR), reconfigurable class-AB/D audio power amplifier is designed for direct battery hookup in portable applications. The proposed design employs the on-chip battery voltage tracking common-mode reference (BAVTCMR) generator and the pseudo-differential topology to achieve the high SNR requirement in a hands-free/receiver 2-in-1 loudspeaker. This amplifier can achieve 106 dB/100 dB PSRR at 217 Hz and 1 kHz, respectively. In receiver mode, this design can drive 46 mW into an 8- Ω load. A true 100-dB SNR is also achieved when a global system for mobile communications (GSM) is generating ripple noise on the system power lines. Reconfiguration is implemented by employing the low-noise operational amplifier (opamp) and capacitors in the class-D integrator as the first gain stage and the compensation capacitors, respectively, in a class-AB amplifier. Hence, the hardware redundancy and the design complexity are both minimized. Fabricated with 0.153-μm CMOS technology, 74-dB/76-dB THD are achieved for class-AB and class-D, respectively. More than 90% efficiency is achieved in class-D mode operation. The maximum output power at 1% THD is 1.23 W. The active area of the prototype class-AB/D amplifier is 0.5 mm2.

A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration

A 12-b 30-MS/s pipelined ADC is realized using single-stage, low-gain, class-AB amplifiers, which can dynamically provide the load currents without large static currents. In addition, the amplifiers are power cycled and turned on only during residue amplification to enable further power savings. Nonlinear errors due to finite gain are addressed using a deterministic digital background calibration scheme. The amplifier's transfer function is piecewise modeled in our calibration scheme using three third-order polynomial functions (splines) for low computational overhead. The presented ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near Nyquist. The corresponding figure of merit is 72 fJ/conversion-step.

LDMOS Technology for RF Power Amplifiers

We show the status of laterally diffused metal-oxide-semiconductor (LDMOS) technology, which has been the device of choice for RF power applications for more than one decade. LDMOS fulfills the requirements for a wide range of class AB and pulsed applications, such as base station, broadcast, and microwave. We present state-of-the-art RF performance of the LDMOS transistor measured with a load-pull test setup, achieving class-AB drain efficiencies of 70% at 2 GHz for on-wafer and packaged devices. Furthermore, the results for several class-AB and Doherty amplifier implementations constructed with this technology are shown. As an illustration, a three-way Doherty application is demonstrated, which has a 7.5-dB back-off efficiency of 47% at 1.8 GHz with a peak power of 700 W and linearity numbers better than -65 dBc.

Complex-Chebyshev Functional Link Neural Network Behavioral Model for Broadband Wireless Power Amplifiers

The Neural Network (NN) based models are commonly used in power amplifier modeling and predistorter design, and seen as a potential alternative to model and compensate broadband power amplifiers (PAs) having medium- to-strong memory effects along with high-order nonlinearity. In this paper, we propose a novel computationally efficient behavior model based on complex-Chebyshev functional link neural network (CCFLNN) suitable for dynamic modeling of wireless PAs. The CCFLNN exhibits a simpler compact structure than the previously reported NNs and can require less computational burden during the learning process since it uses the complex-valued topology and does not need the hidden layers, which exist in most of the conventional neural-network-based models. The proposed approach utilizes the complex-valued inverse QR-decomposition-based recursive least square algorithm to update the weighting coefficients of the CCFLNN model. The proposed model is comparatively compared with a real-valued focused time-delay NN model and a conventional memory polynomial model with respect to computation complexities and modeling performance. The accurate modeling capacity of the CCFLNN model is demonstrated through a full characteristic (working in the strongly nonlinear region) 170-W class AB amplifier driven by a multicarrier WCDMA signal. Furthermore, the proposed model has been applied for linearizing a real PA in multicarrier application. Results obtained from the measurement clearly show that the proposed digital predistorter can eliminate various intensity in-band and out-of band distortions.

Converting a Three-Stage Pseudoclass-AB Amplifier to a True-Class-AB Amplifier

We convert a low-voltage low-transistor-count wide-swing multistage pseudoclass-AB amplifier proposed by Mita et al. to a true-class-AB amplifier. The conversion is made possible using gate-drain feedback to combine two inverting common- source amplifiers to form a single noninverting stage. Both the pseudoclassand true-class-AB amplifiers were fabricated in a 0.5-μm CMOS 2P3M process. They are designed to operate from ±1.25-V supplies at a nominal quiescent current of 175 μA and a minimum phase margin of 45° when driving capacitive loads from 1 to 200 pF and resistive loads from 500 Ω to 1 MΩ. The total com- pensation capacitance of the proposed class-AB amplifier is 12 pF, which is 50% less than the pseudoclass-AB amplifier. The simu- lated unity-gain frequency of the class-AB amplifier is 4.9 MHz at a load of 25 pF||1kΩ, which is 88% higher than that of the pseudoclass-AB amplifier. Experimental measurements show that the proposed amplifier has a maximum total bias current of 175 μA, as compared with 1.05 mA for the pseudoclass-AB am- plifier. Measured slew rates of the proposed amplifier are 2.7 and 3.3 V/μs, twice as much as those of its pseudoclass-AB counterpart.

Efficiency Enhancement of Pico-cell Base Station Power Amplifier MMIC in GaN HFET Technology Using the Doherty Technique

1 Abstract With the growth of smart-phones, the demand for more broadband, data-centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4 generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use nonconstant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10x11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high efficiencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

Switching Optimization for Class-G Audio Amplifiers with Two Power Supplies

This paper presents a system-level method to decrease the power consumption of integrated audio Class-G amplifiers for mobile phones by using the same implementation of the level detector, but by changing the parameters of the switching algorithm. This method uses an optimization based on a simplified model simulation to quickly find the best power supply switching strategy in order to decrease the losses of the internal Class-AB amplifier. Using a few relevant equations of Class-G on the electrical level and by reducing the number of calculation points, this model can dramatically reduce the calculation time to allow power consumption evaluation in realistic case conditions compared to the currently available tools. This simplified model also evaluates the audio quality reproduction thanks to a psycho-acoustic method. The model has been validated by comparing model results and practical measurements on two industrial circuits. This proposed model is used by an optimizer based on a genetic algorithm associated with a pattern search algorithm to find the best power supply switching strategy for the internal Class-AB amplifier. The optimization results improve life-time performance by saving at least 25% in power consumption for typical use-case (1mW) compared to the industrial circuit studied and without losses in audio quality.

Comparison of electromigration simulation in test structure and actual circuit

With the rapid increase in circuit complexity, accurate reliability simulator is necessary as reliability testing for fabricated circuit is progressively more time and resource consuming. Simple 2D electromigration (EM) simulator has many limitations and most of the 3D EM simulations in the literature are using simple line-via structure which is only part of the real circuit structure. In this paper, a thorough comparison between simple 3D line-via structure model and 3D circuit model under different test conditions is performed using class-AB amplifier as an example, and the results showed that simple line-via structure simulation may not always correctly represent the real circuit failure site.

A Physically Meaningful Neural Network Behavioral Model for Wireless Transmitters Exhibiting PM–AM/PM–PM Distortions

Artificial neural networks (ANNs) have been widely used to model wireless transmitter low-pass equivalent behavior. However, previously proposed ANNs either do not account for PM-AM and PM-PM distortions or do not satisfy a fundamental constraint imposed by the bandpass nature of wireless transmitters. The purpose of this work is twofold. First, it is shown that PM-AM and PM-PM distortions observed in wireless transmitters excited by wideband signals can have a significant impact on the performance of their behavioral models. Second, a novel ANN topology for wireless transmitter behavioral modeling is proposed. Contrary to previously published ANNs, this one only generates physically meaningful contributions as well as retaining the ability of accounting for PM-AM and PM-PM distortions. The accuracy of the proposed ANN is then compared with two commonly used ANNs of the same computational complexity and for fitting experimental data measured on a GaN-based class-AB amplifier chain. Improvements of up to 7 dB in NMSE and ACEPR results are achieved if the proposed ANN is used instead of a commonly used ANN that neglects the PM-AM and PM-PM distortions. Furthermore, improvements as high as 16 dB in NMSE and ACEPR are achieved by the proposed ANN in comparison with a traditional ANN that also accounts for the PM-AM and PM-PM distortions but does not satisfy the fundamental odd-parity constraint imposed by the bandpass nature of wireless transmitters.

Performance Evaluation of Peak-to-Average Power Ratio Reduction and Digital Pre-Distortion for OFDM Based Systems

In this paper, we evaluate the effect of applying peak-to-average power ratio (PAPR) reduction and digital pre-distortion (DPD) on two types of radio frequency power amplifiers when an orthogonal frequency division multiplexing (OFDM) signal is used. The power amplifiers under test are a standard class-AB amplifier and a Doherty amplifier. The PAPR reduction methods are based on a state-of-the art convex optimization formulation and on the standard clipping and filtering technique. The DPD method consists of modeling the behavior of the power amplifier using a parallel Hammerstein model, and then extracting the inverse parameters based on the indirect learning architecture. To achieve better DPD performance, extracting the DPD parameters based on multiple-step iterations is investigated. The cases where PAPR reduction and DPD are applied separately and combined are studied and investigated. Power amplifier figures of merit are evaluated. Good performance is shown when combining both pre-processing techniques up to a certain operating point where DPD performance deteriorates due to generation of strong peaks in the signal. In addition, a difference in the power amplifier behavior is reported and analyzed.

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.

A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.