Class AB Amplifier Research Articles

A low-noise class AB amplifier fabricated by 180 nm BCD process for servo circuit of quartz flexible accelerometer

Quartz Flexible Accelerometer (QFA) system has gained extensive utilization in related navigation system due to the high precision, exceptional stability, and rapid response. The operational amplifier as the pivotal component of the analog servo circuit intricately relative to the performance of the QFA system. In this paper, the electrical mechanism of the QFA readout system and the influence of operational amplifier noise on the noise of QFA readout system is studied, a low-noise Class AB amplifier for the servo circuit of QFA readout system designed and fabricated by 180 nm BCD process, and the QFA readout system with the designed amplifier is simulated. The experimental results show that the low-noise amplifier achieved equivalent input current and voltage noise of 5.75pA/sqrt (Hz) and 12.7nV/sqrt (Hz) separately. Simulation results shows the designed QFA servo circuit has achieved resolution of 35 μ g and noise of 2.1 μ g/sqrt (Hz) @1Hz.

A 12-bit Digital-to-Analog Converter for Current Distribution Type

Sensors have a wide range of applications in environmental monitoring, for example, as temperature transmitters in industrial control processes. In order to reduce the chip area and improve the digital-to-analogue conversion accuracy, large loads are driven. This study proposes a current-shunted DAC for sensor interfaces with an R-2R structure, using a Class-AB amplifier to buffer or amplify the signal. Spectre simulation shows that the DAC has a current consumption of 63uA when the supply voltage and reference voltage are 1.8V and can drive a 15pF capacitive load.

CMOS Embedded High-Efficiency Cardiac Pacemakers Design

With the increasing incidence of sudden cardiac death in recent years, the importance of pacemakers has become particularly important. This paper study CMOS circuit design in pacemakers so that they can stay for a long time without charging. Firstly, compared with class A and B amplifier which has low efficiency and high distortion respectively, class AB amplifiers act as a balance between linearity and efficiency, achieving high current drive capability with very low static power consumption. A current mirror based on transduction multiplication to achieve ultra-low current consumption confirms the usefulness of AB amplifiers in pacemakers. This paper design a low power consumption circuit. Firstly, we compare the circuit diagrams of different A, B class amplifiers and analyze their characteristics. Secondly, we analyzed the principle of Class AB amplifier and verified its efficient characteristics. Finally, we studied the effect of this amplifier on a cardiac pacemaker.

An enhanced ultra-wideband single phase hybrid supply envelope tracking modulator for modern wireless communications

This paper presents a Single Phase Hybrid Supply Envelope tracking Modulator (HSEM) for RF-Power Amplifiers (RF-PAs) used in modern wireless communication systems such as 5G and 6G applications. The proposed HSEM consists of an ultra-wideband linear amplifier to track the input signals with several Mega Hertz of bandwidth, a switching amplifier to provide a high-efficiency supply voltage for the main power amplifier, and a new sensing circuit to generate the required voltage for the switching amplifier. The designed HSEM uses a two-stage rail-to-rail linear class-AB amplifier with constant Gm, high gain bandwidth (GBW), high slew rate (SR), and good phase margin (PM). Most conventional modulators use a sensing resistor or a resistor structure that increases the output ripple and the power loss. The proposed structure uses a linear amplifier output stage sensing circuit and a hysteresis low power current comparator without any resistors, external capacitors, filters, or multi-phase modulator structures. Additionally, using a current comparator eliminates the need for an external reference voltage or a current-to-voltage converter. The proposed structure does not need to remove the switching ripple through the linear amplifier, leading to a more relaxed linear amplifier design. A comprehensive analysis and guide on how to optimally select the inductor values, and the mathematical equation for the switching frequency of the hybrid modulator is given. The efficiency of the proposed structure is 84.3 %, and the maximum output power is 27.3dBm. The average output ripple is 4.16 mV in the wide range of the input voltages, and its minimum is 0.4 mV. In addition, the new structure can track a signal with 400 MHz bandwidth with FOM of the HSEM about 18. The proposed modulator is suitable for broadband and emerging telecommunications applications such as 5G and 6G, and as a power supply for RF power amplifiers. The proposed HSEM is evaluated with TSMC 180 nm CMOS technology parameters.

Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology

<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

Design of 0.1‐mV zero‐g and 200‐μg/√Hz capacitance accelerometer with high sensitivity readout circuit with time‐to‐digital convertor applied to finger tremor of neurodegenerative disease

AbstractFinger tremors occur in the early stage of brain disease such Parkinson's syndrome and dementia and are usually detected using inertial sensors such as triaxial gyroscopes or triaxial accelerometer to detect the finger tremor. But finger tremoring is a low‐acceleration and low‐frequency oscillation, and conventional gyroscopes and accelerometer cannot be used for the finger tremor detection. In this paper, we design and implement a single‐axis capacitance MEMS accelerometer, and a readout circuit with a Class AB amplifier with chopper technique and a time‐to‐digital convertor circuit with 1 bit for movement direction count and 8 bits for movement duration count. The proposed accelerometer and readout circuit can achieve 0.1‐mV low offset drift and 53‐mg offset at zero‐g, 200‐μg/√Hz noise density, and 720‐mV/g sensitivity. Mounting the proposed MEMS sensor on tremor index finger, measurement from time‐to‐digital convertor circuit shows twice time durations and a distinct count of changes in tremor finger movement. Monitoring movement durations through the proposed time‐to‐digital convertor circuit, it enables the clinicians to understand in a simple way whether finger tremors are associated with early dementia or Parkinson's syndrome, rather than just conventional amplitude voltage.

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.

A 2 mA PA Driver Capable of Handling 1μF Load Capacitance with a Three-Stage Class-AB Rail-To-Rail Amplifier

In this paper, a three-stage rail-to-rail class-AB amplifier for GaAs/GaN PA driver in radar transmitter components is achieved using a proposed frequency compensation scheme in 0.35 μm CMOS technology. Meanwhile, a negative voltage reference is proposed with low un-trimmed spread by employing level shift technique. The PA driver capable of handling load capacitance ranging from no load to 1uF only consumes 2 mA of quiescent current while delivering a peak current of 100 mA to the load with −90 dB THD. The core area occupies 2.4mm2.

High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

A 40 MHz Bandwidth, 91% Peak Efficiency, 2.5 W Output Power Supply Modulator With Dual-Mode Sigma–Delta Control and Adaptive Biasing Amplifier for Multistandard Communications

The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One shortcoming of state-of-the-art ET PAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma–Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W.

The influence of energy recovery on the overall efficiency of acoustic sources at low frequencies

This paper defines a criterion called the overall efficiency (OE) for evaluating the efficiency of acoustic sources. In practice, the conventional efficiency (CE), is not capable of giving a comprehensive overview of the power consumption, especially in the connected amplifier drivers. The reason for this is that the CE is defined based on the nominal input electrical power. The nominal input electrical power is defined as the real part of the power that is delivered by the electrical amplifier to the actuation unit of an acoustic source. Therefore, power loss in the amplifier unit is not included in the CE definition. With the aid of the OE criterion, the effect of power loss in the connected amplifier units is taken into account. In particular, the application of the OE is crucial for acoustic sources that operate in a low frequency range. This is due to the reactive nature of power in both actuators and connected amplifiers. In the current paper, various combinations of amplifiers and actuators are studied. In particular, voice coil actuators and piezoelectric stack elements including both Lead Zirconate Titanate (PZT) ceramics and single crystal Lead Zirconate Niobate-Lead Titanate (PZN-PT) piezoelectric materials are investigated. In addition, the effect of a connected power driver is investigated. A class AB and a class D amplifier are studied respectively as analogue and switching amplifiers. Unlike a class AB amplifier, a class D amplifier is capable of energy recovery. A perforated flat acoustic source is examined in this paper as a practical example to verify the OE criterion. The numerical simulation on a thin acoustic source shows that for a single actuator, thanks to energy recovery, the OE is higher in a class D amplifier than that in a class AB amplifier. This study reveals that if a class D amplifier is the driver, using piezoelectric actuators results in a higher OE compared to using a voice coil actuator. Measurements on the sample acoustic source verify the numerical results presented in the current study.

Design of Class D Audio Power Amplifier Suitable to Hearing Aid Devices

An amplifier is an electronic circuit that improves the strength of the signal. Using an amplifier in an audio system is essential to improve the strength of the signal. Based on different applications and specifications different types of amplifiers are used. Generally in an audio system, the input signal is amplified to a minimum required power level and then the speaker is driven by it. Conventionally, the output stage of an audio amplifier uses Class-A or Class-AB operating in a linear transfer region. The power efficiency of the Class-D amplifier has a better output efficiency compared to Class-A and Class-AB amplifiers, and its distortion is lower than that of the Class-C amplifier. This is based on a known fact that the Class D amplifier has a switching action in which the transistors are either completely on or off. As a result, the amplification is achieved with no power dissipation. Hence, the size of the amplifier can be highly reduced and a smaller heat sink is required. This paper focuses on designing a Class-D power amplifier which is suitable for hearing aid devices to deliver 500mW output power and for the THD to be less than 3%. The circuit implementation is done using UMC high voltage 0.18μm technology. This amplifier consists of three stages such as the modulation stage, the driver stage, the bridge stage, and the demodulation stage. Unfortunately, the Class-D power amplifier has inherent non-linear distortion problems, which is more significant than conventional audio power amplifiers. In this thesis, negative feedback is employed to reduce THD. Without feedback, the THD is obtained as above 3%. By employing feedback, the THD was reduced by 1.96dB. This design result is discussed and through to realization; whereupon the effectiveness of each of the implementation is evaluated.

Realization with Fabrication of Double-Gate MOSFET Based Class-AB Amplifier

This research work designs the class-AB amplifier with the application of Double-Gate (DG) MOSFET, which provides insight on how the amplifier can be utilized, in accordance with its future design. Main consideration is the use of DG MOSFET in audio amplifier design, for its low power and low noise application, voltage regulation for high to low power, etc. The challenge of this design is an attempt to use the DG MOSFET as prominent component, to demonstrate it as a usable in common electronic applications. Model of class-AB amplifier using the DG MOSFET (for audio amplifier) has been designed, fabricated, and thereafter analysed with its frequency and power characteristics. This proposed design with 2 Wrms audio amplifier drives a nominal 8 Ω load by a 100 mVrms input signal, for the typical audio frequency range of 20 Hz – 20 kHz.

A Bidirectional Current-Mirror-Based Potentiostat Using a Slice-Based Class-AB Amplifier

A pico-ampere sensitive electrochemical sensor signal acquisition chain consisting of a multi-channel bidirectional current-mirror based potentiostat and a multiplexed current-input delta-sigma ($\Delta \Sigma$) ADC is presented. Slice-based class-AB amplifiers with output stage current replication using reconfigurable current-mirrors enable bidirectional current sensing over a range of five decades. The replicated current is digitized by the ADC. The proposed circuit achieves a minimum detectable current of 91.7 pA, resulting in a dynamic range of 147 dB for sensor currents up to $\pm$1 mA. The potentiostat is operated at a 3 V supply, the ADC at 1.5 V. The static power consumption of a single interface channel depends on the number of active amplifier slices and is between 14.1 $\mu$W and 39.3 $\mu$W. The highest power efficiency among similar systems and the low voltage headroom consumption of less than 500 mV enables a versatile use of the interface for multiple sensing applications.

Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications

This paper introduces for the first time all the steps required in the optimal design of carbon nanotube field-effect transistor (CNTFET)-based second generation current conveyor (CCII) using transconductance-to-drain current ratio ([Formula: see text]) technique for low-voltage (LV) and low-power (LP) applications. The [Formula: see text] technique is a well-established methodology for CMOS analog IC design. However, the difference between CMOS and CNTFET is that CMOS has continuous width while the width of CNTFET is discrete and depends on different parameters like the number of tubes, pitch and diameter ([Formula: see text]) of the carbon nanotube (CNT). Therefore, there is a need for a design technique by which one can easily design analog circuits using CNTFETs. The CCII is based on two-stage op-amp and two inverters used as class AB amplifiers. The performance of CCII has been extensively examined in terms of DC, AC and transient responses of node voltages, branch currents and node impedances using HSPICE simulations. The CCII operates at [Formula: see text]0.5[Formula: see text]V and has 172[Formula: see text][Formula: see text]W of power consumption. The designed CCII provides very high 3-dB bandwidth (BW) for current gain ([Formula: see text][Formula: see text]GHz as well as voltage gain ([Formula: see text][Formula: see text]GHz.

Ultra-low power two-stage class-AB recycling double folded cascode OTA

This paper presents an ultra-low power two-stage class-AB recycling double folded cascode (RDFC) fully differential operational transconductance amplifier (OTA) with high DC gain, unity gain frequency, slew rate, and common-mode rejection ratio (CMRR). Design and simulation of the proposed OTA is done in a 0.18-μm standard CMOS technology with a 1 V supply voltage. In this design, all transistors operate in weak inversion. A new RDFC structure with two separate paths to increase the gain and reduce the power consumption is used in the first stage of the proposed OTA. In the second stage, a class-AB amplifier is employed to improve the CMRR, DC gain and slew rate. Also, an output current control unit is included in the first stage to reduce power consumption. The use of the same proper bias circuit for the output current control unit and Miller resistor transistors establishes robust design against the process, voltage, and temperature (PVT) variations and reduces the power consumption. Post-layout simulation results of the proposed OTA demonstrate that it has a good performance over the previous state of the arts with DC gain of 136.8 dB, power consumption of 205.8 nW, and unity gain frequency of 141.7 kHz for a capacitive load of 2 × 7.5 pF.

Far-Field-Based Nonlinear Optimization of Millimeter-Wave Active Antenna for 5G Services

This paper presents the design and characterization of millimeter-wave (28/38 GHz), circularly polarized (CP) active antennas, suitable for future 5G services. By augmenting the modeling capabilities of commercially available nonlinear CAD tools, the active antenna design can simultaneously optimize figures of merits for both radiation and nonlinear (NL) performance. The radiating part is computed and optimized layoutwise by means of an artificial neural network (ANN), suitably trained off-line. For the NL design purpose, the harmonic neural network (HNN) of the antenna is subsequently implemented as a standard circuit component, to include the antenna behavior at all the harmonics of its NL regime. This allows avoiding time-consuming electromagnetic (EM)-simulations in the harmonic balance optimization loop. In this way, a well-defined interface between the antenna and the amplifier can be avoided. To demonstrate the effectiveness of the design approach, one active integrated antenna (AIA), consisting of a class AB amplifier feeding a CP patch at 38 GHz, has been fabricated with the standard 0.1- $\mu \text{m}$ AlGaAs-InGaAs pHEMT technology and extensively measured with respect to both the electrical and radiation performances. To reduce fabrication costs, hybrid integration of the antenna and amplifier connection is used, and the antenna is incorporated into the main PCB.

Class AB amplifier with enhanced slew rate and GBW

SummaryThe design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power‐efficient adaptive biasing circuit and a class AB current follower using the quasi‐floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5‐μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small‐signal performance.

A 1-mW Class-AB Amplifier With −101 dB THD+N for High-Fidelity 16 $\Omega$ Headphones in 65-nm CMOS

A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves −101.4-dB total harmonic distortion plus noise (THD+N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a $16\Omega \|0.33$ -nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 $\times $ improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power $\times $ THD+N[%])). It occupies 0.16 mm 2 in a standard 65-nm CMOS.

Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier

This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of $10.2~\mu \text{A}$ . It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of $0.22~\mu \text{s}$ is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of $0.1~\mu \text{s}$ .